Manufacturing method of semiconductor light emitting device

Patent metadata

Field	Value
Publication number	US-11264532-B2
Application number	US-201916727496-A
Country	US
Kind code	B2
Filing date	Dec 26, 2019
Priority date	Jul 8, 2019
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

Provided a manufacturing method of a semiconductor light emitting device including forming a plurality of light emitting cells that are separated on a first substrate, forming a first planarization layer by providing an insulating material on the plurality of light emitting cells, forming a second planarization layer by providing a photoresist on the first planarization layer to have a flat upper surface, and soft baking the photoresist, and dry etching the second planarization layer to a predetermined depth to expose a portion of the first planarization layer provided on the plurality of light emitting cells, and a portion of the second planarization layer remaining between the plurality of light emitting cells on the first planarization layer, wherein forming the second planarization layer and dry etching are repeated at least once to remove the portion of the second planarization layer provided between the plurality of light emitting cells.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor light emitting device, the manufacturing method comprising:
forming a plurality of light emitting cells that are individually separated on a first substrate;
forming a first planarization layer by providing an insulating material on the plurality of light emitting cells, a thickness of the first planarization layer being greater than a thickness of the plurality of light emitting cells;
forming a second planarization layer by providing a photoresist on the first planarization layer to have a flat upper surface, and soft baking the photoresist; and
dry etching the second planarization layer to a predetermined depth to expose a portion of the first planarization layer provided on the plurality of light emitting cells, and a portion of the second planarization layer remaining between the plurality of light emitting cells on the first planarization layer,
wherein the forming the second planarization layer and the dry etching are repeated in an order of forming the second planarization layer and dry etching at least once to remove the portion of the second planarization layer provided between the plurality of light emitting cells.

2. The manufacturing method of the semiconductor light emitting device of claim 1 , wherein forming the plurality of light emitting cells comprises:
sequentially forming a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer on the first substrate; and
partially etching the first conductivity-type semiconductor layer, the active layer, and the second conductivity-type semiconductor layer, respectively, to expose a portion of the first substrate.

3. The manufacturing method of the semiconductor light emitting device of claim 2 , wherein the plurality of light emitting cells comprise a plurality of light emitting structures which share the first conductivity-type semiconductor layer, respectively and in which the active layer and the second conductivity-type semiconductor layer are separately provided.

4. The manufacturing method of the semiconductor light emitting device of claim 3 , further comprising forming a connection electrode connecting adjacent light emitting structures of the plurality of light emitting structures.

5. The manufacturing method of the semiconductor light emitting device of claim 2 , further comprising:
forming a first electrode on the first conductivity-type semiconductor layer and forming a second electrode on the second conductivity-type semiconductor layer, after forming the plurality of light emitting cells.

6. The manufacturing method of the semiconductor light emitting device of claim 1 , wherein the first substrate is a growth substrate.

7. The manufacturing method of the semiconductor light emitting device of claim 1 , wherein the first planarization layer and the second planarization layer have an etching selectivity of 1:0.1 to 1:2.0 with respect to the dry etching.

8. The manufacturing method of the semiconductor light emitting device of claim 1 , wherein the insulating material is formed of silicon oxide or silicon nitride.

9. The manufacturing method of the semiconductor light emitting device of claim 1 , further comprising bonding a second substrate on the first planarization layer after the dry etching.

10. The manufacturing method of the semiconductor light emitting device of claim 9 , wherein the first substrate and the second substrate are made of a same composition material.

11. The manufacturing method of the semiconductor light emitting device of claim 1 , wherein forming the first planarization layer comprises filling a separation space provided between the plurality of light emitting cells.

12. A manufacturing method of a semiconductor light emitting device, the manufacturing method comprising:
forming a semiconductor laminate by sequentially stacking a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer on a growth substrate;
forming a plurality of light emitting cells on a mesa region partitioned by a separation space that is formed by etching a portion of the semiconductor laminate to expose the growth substrate, the plurality of light emitting cells comprising a plurality of light emitting structures that share the first conductivity-type semiconductor layer, and in which the active layer and the second conductivity-type semiconductor layer are separately provided;
forming a first planarization layer by providing an insulating material on the plurality of light emitting cells and the separation space, a thickness of the first planarization layer being greater than a thickness of the semiconductor laminate;
forming a second planarization layer on the first planarization layer by providing a photoresist on the first planarization layer and soft baking the photoresist; and
dry etching the second planarization layer to a predetermined depth from an upper surface direction of the second planarization layer to expose a portion of the first planarization layer overlapping the mesa region, and a portion of the second planarization layer provided between the plurality of light emitting cells remaining on the first planarization layer,
wherein the forming the second planarization layer and the dry etching are repeated in an order of forming the second planarization layer and dry etching at least once to remove the portion of the second planarization layer provided between the plurality of light emitting cells.

13. The manufacturing method of the semiconductor light emitting device of claim 12 , wherein a height of a lowest region of an upper surface of the first planarization layer is 10% or more higher than a height of a highest region of an upper surface of the second conductivity-type semiconductor layer.

14. The manufacturing method of the semiconductor light emitting device of claim 12 , wherein an etching rate of the insulating material is substantially equal to an etching rate of the photoresist.

15. The manufacturing method of the semiconductor light emitting device of claim 12 , wherein the growth substrate is a silicon substrate.

16. A manufacturing method of a semiconductor light emitting device, the manufacturing method comprising:
forming a plurality of light emitting cells respectively comprising a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer that are sequentially stacked on a growth substrate, and partitioned by a separation space in which the growth substrate is exposed;
forming a first planarization layer comprising an upper surface that is higher than an upper surface of the second conductivity-type semiconductor layer by depositing an insulating material on the plurality of light emitting cells and the separation space;
forming a second planarization layer by providing a photoresist on the first planarization layer and soft baking the photoresist; and
dry etching the second planarization layer to a predetermined depth from an upper surface direction of the second planarization layer to expose a portion of the second planarization layer overlapping the plurality of light emitting cells of the first planarization layer, and a portion of the second planarization layer provided between the plurality of light emitting cells remaining on the first planarization layer,
wherein the forming the second planarization layer and the dry etching are repeated in an order of forming the second planarization layer and dry etching at least once to remove the portion of the sec

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Daeyeop
• Park Kiwon
• Kim Jaeyoon
• Kim Sungjoon
• Kim Inho

Classifications

• H10W90/00

  Package configurations · CPC title

• H10H20/83

  Electrodes · CPC title

• H10H29/142 Primary

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10H20/01 Primary

  Manufacture or treatment · CPC title

• H10H20/0364

  of interconnections · CPC title