Semiconductor device having metal interconnects with different thicknesses

Patent metadata

Field	Value
Publication number	US-11264329-B2
Application number	US-201616074142-A
Country	US
Kind code	B2
Filing date	Apr 1, 2016
Priority date	Apr 1, 2016
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

First claim

What is claimed is:

1. An apparatus comprising:
a first metal layer having a first thickness along a depth dimension and a second thickness along the depth dimension, wherein the second thickness is less than the first thickness, and the first metal layer comprises a first interconnect having the first thickness;
a second metal layer;
a dielectric material extending between the first and second metal layers and directly contacting the first and second metal layers, the dielectric material comprising a via extending through the dielectric material; and
a metal material of the via to directly contact the first interconnect and the second metal layer.

2. The apparatus of claim 1 , wherein:
the first metal layer further comprises a second interconnect parallel to the first interconnect; and
the second interconnect has the first thickness.

3. The apparatus of claim 2 , wherein:
the first metal layer further comprises a third interconnect and a fourth interconnect parallel to the fourth interconnect;
the second interconnect is spaced apart from the first interconnect by a first distance; and
the fourth interconnect is spaced apart from the third interconnect by a second distance less than the first distance.

4. The apparatus of claim 3 , wherein the first distance is substantially the sum of the first thickness and the second distance less a cross-sectional width of the first interconnect.

5. The apparatus of claim 3 , wherein:
the third interconnect has cross-sectional width;
the first interconnect has a cross-sectional width that is greater than the cross-sectional width of the third interconnect; and
the first distance is substantially the sum of the first thickness and the second thickness less a cross-sectional width of the first interconnect.

6. The apparatus of claim 3 , wherein:
the third interconnect has cross-sectional width;
the first interconnect has a cross-sectional width that is substantially the same as the cross-sectional width of the third interconnect; and
the first distance is substantially the sum of the first thickness and the second thickness less a cross-sectional width of the first interconnect.

7. The apparatus of claim 1 , wherein the first interconnect has a substantially uniform cross-sectional width.

8. The apparatus of claim 7 , wherein the cross-sectional width of the first interconnect is less than the first thickness.

9. The apparatus of claim 1 , wherein:
the first metal layer further comprises another interconnect parallel to the first interconnect;
the another interconnect has the second thickness and a cross-sectional width that is substantially the same as a cross-sectional width of the first interconnect.

10. The apparatus of claim 1 , wherein:
the first metal layer further comprises another interconnect parallel to the first interconnect;
the another interconnect has the second thickness and a cross-sectional width that is smaller than a cross-sectional width of the first interconnect.

11. The apparatus of claim 1 , comprising a system-on-chip (SoC) that includes the first metal layer, the second metal layer, the dielectric material and the metal material.

12. A system comprising:
a memory; and
a processor coupled to the memory,
wherein at least one of the processor and the memory includes an apparatus according to claim 1 .

13. An apparatus comprising:
a first metal layer having a first thickness and a second thickness less than the first thickness, wherein the first metal layer comprises:
a first plurality of parallel interconnects, each interconnect of the first plurality of interconnects having a first thickness; and
a second plurality of parallel interconnects, each interconnect of the second plurality of interconnects having a second thickness less than the first thickness;

a second metal layer;
a dielectric material extending between the first and second metal layers and directly contacting the first and second metal layers, the dielectric material comprising a via extending through the dielectric material; and
a metal material of the via to directly contact the second metal layer and at least one of the interconnects of the first plurality of parallel interconnects.

14. The apparatus of claim 13 , wherein:
the first plurality of interconnects has an associated first spacing between adjacent interconnects of the first plurality of parallel interconnects;
the second plurality of interconnects has an associated second spacing between adjacent interconnects of the second plurality of parallel interconnects; and
the second spacing is less than the first spacing.

15. The apparatus of claim 13 , wherein first plurality of interconnects are parallel to a first axis and the thickness of each interconnect of the first plurality of interconnects corresponds a dimension measured along a second axis orthogonal to the first axis.

Assignees

• Intel Corp

Inventors

• Phoa Kinyip
• Lin Jui-Yen
• Nidhi Nidhi
• Jan Chia-Hong

Classifications

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W70/635

  Through-vias · CPC title