Memory cell including multi-level sensing

Patent metadata

Field	Value
Publication number	US-11264094-B2
Application number	US-201815911350-A
Country	US
Kind code	B2
Filing date	Mar 5, 2018
Priority date	Mar 5, 2018
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.

First claim

We claim:

1. An electronic processing system, comprising:
a processor;
multi-level memory communicatively coupled to the processor;
an analog-to-digital converter communicatively coupled to the multi-level memory to convert an analog voltage level of a memory cell of the multi-level memory to a corresponding multi-bit digital value; and
logic communicatively coupled to the multi-level memory and the analog-to-digital converter to:
determine a single-bit value of the memory cell based on the multi-bit digital value, and
adjust the determination of the single-bit value of the memory cell for potential drift of the analog voltage level of the memory cell based on a temporal history of accesses to the memory cell.

2. The system of claim 1 , wherein the logic is further to:
apply error correction to determine the value of the memory cell based on the multi-bit digital value.

3. The system of claim 1 , wherein the logic is further to:
track a history of accesses to the memory cell.

4. The system of claim 3 , wherein the logic is further to:
track the temporal history of accesses to the memory cell for a duration in excess of ten seconds.

5. The system of claim 1 , wherein the multi-level memory comprises a phase change memory.

6. The system of claim 5 , wherein the phase change memory comprises a three dimensional crosspoint memory.

7. A semiconductor apparatus, comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value,
determine a single-bit value of the memory cell based on the multi-bit digital value, and
adjust the determination of the single-bit value of the memory cell for potential drift of the analog voltage level of the memory cell based on a temporal history of accesses to the memory cell.

8. The apparatus of claim 7 , wherein the logic is further to:
apply error correction to determine the value of the memory cell based on the multi-bit digital value.

9. The apparatus of claim 7 , wherein the logic is further to:
track a history of accesses to the memory cell.

10. The apparatus of claim 9 , wherein the logic is further to:
track the temporal history of accesses to the memory cell for a duration in excess of ten seconds.

11. The apparatus of claim 7 , wherein the multi-level memory comprises a phase change memory.

12. The apparatus of claim 11 , wherein the phase change memory comprises a three dimensional crosspoint memory.

13. The apparatus of claim 7 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

14. A method of determining a memory value, comprising:
converting an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value;
determining a single-bit value of the memory cell based on the multi-bit digital value; and
adjusting the determination of the single-bit value of the memory cell for potential drift of the analog voltage level of the memory cell based on a temporal history of accesses to the memory cell.

15. The method of claim 14 , further comprising:
applying error correction to determine the value of the memory cell based on the multi-bit digital value.

16. The method of claim 14 , further comprising:
tracking a history of accesses to the memory cell.

17. The method of claim 16 , further comprising:
tracking the temporal history of accesses to the memory cell for a duration in excess of ten seconds.

18. The method of claim 14 , wherein the multi-level memory comprises a phase change memory.

19. The method of claim 18 , wherein the phase change memory comprises a three dimensional crosspoint memory.

Assignees

• Intel Corp

Inventors

• Querbach Bruce
• Connor Christopher

Classifications

• G11C27/005

  with non-volatile charge storage, e.g. on floating gate or MNOS · CPC title

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C14/0045

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title