Processor checking method, checking device and checking system

Patent metadata

Field	Value
Publication number	US-11263314-B2
Application number	US-201916245898-A
Country	US
Kind code	B2
Filing date	Jan 11, 2019
Priority date	Feb 9, 2018
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

The disclosure provides a processor checking method, a checking device and a checking system. The method includes acquiring a first access record of the processor to a first memory during a running process, the first access record including reading-operation information; acquiring a second access record of a checking device to a second memory during a replay process, the second access record including first reading-operation information, the first reading-operation information being reading-operation information corresponding to a case in which a first access of the checking device to a same address during the replay process is a reading operation, and determining, based on the first access record and the second access record, whether or not the processor reads during the running process a memory address that is not any one of addresses included in the second access record.

First claim

What is claimed is:

1. A processor checking method, comprising:
acquiring a first access record of a processor to a first memory during a running process, the first access record comprising reading-operation information;
acquiring a second access record of a checking device to a second memory during a replay process, wherein the checking device executes a task of the running process in a manner conforming to predefined behavior during the replay process, wherein the predefined behavior is a hardware behavior standard of the processor, wherein the second access record comprises first reading-operation information, the first reading-operation information comprising the reading-operation information corresponding to a case in which a first access of the checking device to a same address during the replay process is a reading operation;
determining, during the running process, based on the first access record and the second access record, whether the processor reads a memory address that is not one or more addresses included in the second access record; and
determining whether data stored at the memory address is sensitive data predefined by a user, according to a data format of the data stored at the memory address, when the processor reads during the running process the memory address that is not the one or more addresses included in the second access record.

2. The method according to claim 1 , wherein when the processor is a multi-core processor, the first access record further comprises an identifier of a processor core to which the reading-operation information relates.

3. The method according to claim 1 , further comprising: saving relevant operation information about reading the memory address and issuing a security forewarning message to the user, when the processor reads during the running process the memory address that is not the one or more addresses included in the second access record.

4. The method according to claim 1 , further comprising:
determining whether the memory address falls within a preset address range, when the processor reads during the running process the memory address that is not the one or more addresses included in the second access record.

5. The method according to claim 4 ,
wherein when the processor is a multi-core processor, the first access record further comprises an identifier of a processor core to which the reading-operation information relates.

6. The method according to claim 4 , further comprising:
saving relevant operation information associated with reading the memory address and issuing a security forewarning message to the user, when the processor reads during the running process the memory address that is not the one or more addresses included in the second access record.

7. The method according to claim 1 , further comprising:
outputting the reading-operation information corresponding to the memory address to optimize a corresponding program code, when the processor reads during the running process the memory address that is not the one or more addresses included in the second access record; or
determining a position where the reading-operation information corresponding to the memory address is executed in a program, and outputting information of the position to optimize the corresponding program code, when the processor reads during the running process the memory address that is not the one or more addresses included in the second access record.

8. The method according to claim 1 , further comprising:
determining whether a behavior of the processor reading the memory address is an unauthorized operation, when the processor reads during the running process the memory address that is not the one or more addresses included in the second access record.

9. The method according to claim 1 ,
wherein when the processor is a multi-core processor, the first access record further comprises an identifier of a processor core to which the reading-operation information belongs.

10. The method according to claim 1 , further comprising:
saving relevant operation information about reading the memory address and issuing a security forewarning message to a user, when the processor reads during the running process the memory address that is not the one or more addresses included in the second access record.

11. The method according to claim 1 ,
wherein instructions for executing the method are stored in a non-transitory computer readable storage medium.

12. A checking system for checking a processor to be checked, comprising:
one or more checking processors; and a storage configured to store one or more programs,
wherein the one or more checking processors are configured to execute a processor checking method when the one or more programs are executed by the one or more checking processors,
wherein the processor checking method comprises:
acquiring a first access record of a processor to a first memory during a running process, the first access record comprising reading-operation information;
acquiring a second access record of a checking device to a second memory during a replay process, wherein the checking device executes a task of the running process in a manner conforming to predefined behavior during the replay process, wherein the predefined behavior is a hardware behavior standard of the processor, wherein the second access record comprises first reading-operation information, the first reading-operation information comprising the reading-operation information corresponding to a case in which a first access of the checking device to a same address during the replay process is a reading operation;
determining, during the running process, based on the first access record and the second access record, whether the processor reads a memory address that is not one or more addresses included in the second access record; and
determining whether data stored at the memory address is sensitive data predefined by a user, according to a data format of the data stored at the memory address, when the processor reads during the running process the memory address that is not the one or more addresses included in the second access record.

Assignees

• Univ Tsinghua

Inventors

• Liu Leibo
• Luo Ao
• Yin Shouyi
• Wei Shaojun

Classifications

• G06F21/52 Primary

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/35

  Indirect addressing · CPC title

• G06F21/552

  involving long-term monitoring or reporting · CPC title

• G06F21/54 Primary

  by adding security routines or objects to programs · CPC title