Error recovery for intra-core lockstep mode

Patent metadata

Field	Value
Publication number	US-11263073-B2
Application number	US-201816641377-A
Country	US
Kind code	B2
Filing date	Aug 30, 2018
Priority date	Oct 5, 2017
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

An apparatus has a processing pipeline ( 2 ) comprising an execute stage ( 30 ) and at least one front end stage ( 10 ), ( 20 ), ( 25 ) for controlling which micro operations are issued to the execute stage. The pipeline has an intra-core lockstep mode of operation in which the at least one front end stage ( 10 ), ( 20 ), ( 25 ) issues micro operations for controlling the execute stage ( 30 ) to perform main processing and checker processing. The checker processing comprises redundant operations corresponding to associated main operations of at least part of the main processing. Error handling circuitry ( 200 ), ( 210 ) is responsive to the detection of a mismatch between information associated with given checker and main operations to trigger a recovery operation to correct an error and continue forward progress of the main processing.

First claim

The invention claimed is:

1. An apparatus comprising:
a processing pipeline comprising an execute stage to execute data processing in response to micro-operations, and at least one front end stage to control which micro-operations are issued to the execute stage in dependence on program instructions;
said processing pipeline having an intra-core lockstep mode of operation in which said at least one front end stage is configured to issue micro-operations for controlling the execute stage to perform main processing and checker processing, the checker processing comprising redundant operations corresponding to associated main operations of at least part of the main processing; and
error handling circuitry responsive to detection of a mismatch between information associated with a given checker operation and an associated main operation, to trigger a recovery operation to correct an error and continue forward progress of said main processing on said execute stage.

2. The apparatus according to claim 1 , wherein the error handling circuitry comprises result comparing circuitry to detect said mismatch between results of the given checker operation and the associated main operation.

3. The apparatus according to claim 1 , wherein the recovery operation comprises flushing from the processing pipeline at least one in-flight micro-operation corresponding to, or dependent on, said given checker operation and the associated main operation for which the mismatch was detected, and re-issuing said at least one in-flight micro-operation for execution by the execute stage.

4. The apparatus according to claim 1 , wherein the recovery operation comprises flushing all in-flight micro-operations from the processing pipeline and reissuing the flushed micro-operations for execution by the execute stage.

5. The apparatus according to claim 1 , wherein the processing pipeline comprises a writeback stage to defer writeback of a result of the given checker operation or the associated main operation to register state storage until both said given checker operation and the associated main operation have been executed and results of said given checker operation and the associated main operation are determined to match.

6. The apparatus according to claim 5 , wherein the writeback stage comprises pair identifying circuitry to identify a pair of micro-operations corresponding to a checker operation and the associated main operation.

7. The apparatus according to claim 5 , wherein said at least one front end stage is configured to allocate respective pair identifiers to micro-operations issued to the execute stage, with a given checker micro-operations corresponding to the given checker operation and an associated main micro-operation corresponding to the associated main operation allocated matching pair identifiers.

8. The apparatus according to claim 5 , wherein the processing pipeline comprises a commit buffer comprising a plurality of pairs of buffer slots, each buffer slot to buffer an in-flight micro-operation until its result is written back to the register state storage by the writeback stage, and the processing pipeline is configured to allocate a given checker micro-operations corresponding to the given checker operation to a first buffer slot in a given one of said plurality of pairs of buffer slots and to allocate an associated main micro-operation corresponding to the associated main operation to a second buffer slot of said given one of said plurality of pairs of buffer slots.

9. The apparatus according to claim 6 , wherein the pair identifying circuitry is configured to identify the pair of micro-operations based on a comparison of opcodes and operand identifiers associated with the pair of micro-operations.

10. The apparatus according to claim 1 , comprising a plurality of registers, wherein on performing a load operation to load data from a data store to a target register in response to the main processing when operating in the intra-core lockstep mode, the processing pipeline is configured to also write the loaded data to a checker region of the target register or to another register for access by a checker operation corresponding to a main operation which accesses the target register.

11. The apparatus according to claim 1 , wherein said error handling circuitry comprises stored value comparing circuitry to detect said mismatch between a pair of stored data values used for said given checker operation and the associated main operation respectively.

12. The apparatus according to claim 11 , wherein said stored data values comprise architectural state stored in registers.

13. The apparatus according to claim 11 , wherein said stored data values comprises control data stored in a queue structure.

14. The apparatus according to claim 11 , wherein at least one of said pair of stored data values is associated with an error detecting code.

15. The apparatus according to claim 14 , wherein when a mismatch is detected between the pair of stored data values, the error handling circuitry is configured to detect, based on the error detecting code associated with at least one of said pair of stored data values, which of the pair of stored data values is erroneous, and to correct the erroneous stored value using the other of the pair of stored data values.

16. The apparatus according to claim 15 , wherein after the erroneous stored value is corrected, the stored value comparing circuitry is configured to repeat the detection of whether there is a mismatch between the pair of stored data values.

17. The apparatus according to claim 14 , wherein when a match is detected between the pair of stored data values, the error handling circuitry is configured to trigger recomputation of the error detecting code associated with said at least one of said pair of stored data values.

18. The apparatus according to claim 14 , wherein only one of the pair of stored data values is associated with the error detecting code.

19. The apparatus according to claim 1 , wherein the error handling circuitry has:
a recovery mode in which the error handling circuitry is responsive to detection of said mismatch to perform said recovery operation; and
an abort mode in which the error handling circuitry is responsive to detection of said mismatch to abort processing of said main processing on said processing pipeline.

20. The apparatus according to claim 19 , comprising a configuration storage element to store an error handling mode setting value indicative of whether the error handling circuitry is to operate in the recovery mode or the abort mode.

21. The apparatus according to claim 1 , comprising an error counter to count a number of times the recovery operation is performed by the error handling circuitry.

22. The apparatus according to claim 21 , wherein the error handling circuitry is configured to abort processing of said main processing on said processing pipeline when the error counter indicates that the recovery operation has been performed more than a threshold number of times.

23. The apparatus according to claim 21 , comprising a plurality of processors, at least one of said processors comprising said processing pipeline and said error handling circuitry, wherein the error handling circuitry is configured to trigger switching of processing of said main processing to another processor when the error counter indicates that the recovery operation has been performed more than a threshold number of times.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Boettcher Matthias Lothar
• Eyole Mbou
• VENU Balaji

Classifications

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F11/165

  with continued operation after detection of the error · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title

• G06F11/1629 Primary

  Error detection by comparing the output of redundant processing systems · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title