Automatic memory overclocking

Patent metadata

Field	Value
Publication number	US-11262924-B2
Application number	US-201916729702-A
Country	US
Kind code	B2
Filing date	Dec 30, 2019
Priority date	Dec 30, 2019
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

Automatic memory overclocking, including: increasing a memory frequency setting for a memory module until a memory stability test fails; determining an overclocked memory frequency setting including a highest memory frequency setting passing the memory stability test; and generating a profile including the overclocked memory frequency setting.

First claim

What is claimed is:

1. A method of automatic memory overclocking, the method comprising:
increasing a memory frequency setting for a memory module until a memory stability test fails;
determining an overclocked memory frequency setting comprising a highest memory frequency setting passing the memory stability test;
determining one or more overclocked memory timing settings comprising one or more memory timing settings corresponding to the overclocked memory frequency setting; and
generating a profile comprising the overclocked memory frequency setting and the one or more overclocked memory timing settings.

2. The method of claim 1 , wherein the one or more memory timing settings comprise one or more of: a Column Access Strobe (CAS) latency, a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Write), a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Read), a Row Precharge Time, and/or a Row Active Time.

3. The method of claim 1 , further comprising:
determining one or more subtiming settings based on the overclocked memory frequency setting and the one or more overclocked memory timing settings; and
wherein generating the profile comprises including the one or more subtiming settings in the profile.

4. The method of claim 3 , wherein the one or more subtiming settings are based on one or more rules applied to the overclocked memory frequency setting and/or the one or more memory timing settings.

5. The method of claim 1 , further comprising storing the profile in a storage location.

6. The method of claim 5 , further comprising:
loading the profile from the storage location; and
applying the profile to the memory module.

7. An apparatus for automatic memory overclocking, the apparatus configured to:
increase a memory frequency setting for a memory module until a memory stability test fails;
determine an overclocked memory frequency setting comprising a highest memory frequency setting passing the memory stability test;
determine one or more overclocked memory timing settings comprising one or more memory timing settings corresponding to the overclocked memory frequency setting; and
generate a profile comprising the overclocked memory frequency setting and the one or more overclocked memory timing settings.

8. The apparatus of claim 7 , wherein the one or more memory timing settings comprise one or more of: a Column Access Strobe (CAS) latency, a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Write), a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Read), a Row Precharge Time, and/or a Row Active Time.

9. The apparatus of claim 7 , further configured to: determine one or more subtiming settings based on the overclocked memory frequency setting and the one or more overclocked memory timing settings; and wherein generating the profile comprises including the one or more subtiming settings in the profile.

10. The apparatus of claim 9 , wherein the one or more subtiming settings are based on one or more rules applied to the overclocked memory frequency setting and/or the one or more memory timing settings.

11. The apparatus of claim 7 , further configured to store the profile in a storage location.

12. The apparatus of claim 11 , further configured to:
load the profile from the storage location; and
apply the profile to the memory module.

13. A computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising computer program instructions for automatic memory overclocking that, when executed, cause a computer to perform steps comprising:
increasing a memory frequency setting for a memory module until a memory stability test fails;
determining an overclocked memory frequency setting comprising a highest memory frequency setting passing the memory stability test;
determining one or more overclocked memory timing settings comprising one or more memory timing settings corresponding to the overclocked memory frequency setting; and
generating a profile comprising the overclocked memory frequency setting and the one or more overclocked memory timing settings.

14. The computer program product of claim 13 , wherein the one or more memory timing settings comprise one or more of: a Column Access Strobe (CAS) latency, a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Write), a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Read), a Row Precharge Time, and/or a Row Active Time.

15. The computer program product of claim 13 , wherein the steps further comprise:
determining one or more subtiming settings based on the overclocked memory frequency setting and the one or more overclocked memory timing settings; and
wherein generating the profile comprises including the one or more subtiming settings in the profile.

16. The computer program product of claim 15 , wherein the one or more subtiming settings are based on one or more rules applied to the overclocked memory frequency setting and/or the one or more memory timing settings.

17. The computer program product of claim 13 , wherein the steps further comprise storing the profile in a storage location.

Assignees

• Advanced Micro Devices Inc

Inventors

• Alverson William R
• Mehra Amitabh
• Harwani Anil
• Ahrens Jerry A
• Ley Grant E
• Joshi Jayesh

Classifications

• G11C2029/5002

  Characteristic · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C29/50012 Primary

  of timing · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title