Current mirror arrangements with semi-cascoding

Patent metadata

Field	Value
Publication number	US-11262782-B2
Application number	US-202016861915-A
Country	US
Kind code	B2
Filing date	Apr 29, 2020
Priority date	Apr 29, 2020
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q 1 and output a mirrored signal at an output transistor Q 2 . The arrangement further includes a semi-cascoding circuit that includes transistors Q 3 , Q 4 , and a two-terminal passive network. The transistor Q 3 is coupled to, and forms a cascode with, the output transistor Q 2 . The transistor Q 4 is coupled to the transistor Q 3 . The base/gate of the transistor Q 3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q 4 is coupled to a bias voltage Vref 1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref 1.

First claim

The invention claimed is:

1. An electronic device, comprising a current mirror arrangement, the current mirror arrangement including:
a current mirror circuit, comprising a first transistor at an input of the current mirror circuit and a second transistor at an output of the current mirror circuit;
a third transistor;
a fourth transistor; and
a two-terminal passive network,
wherein:
each of the first, second, third, and fourth transistors has a first terminal, a second terminal, and a third terminal,
the first terminal of the first transistor is coupled to the first terminal of the second transistor and to the second terminal of the first transistor,
the second terminal of the second transistor is coupled to the third terminal of the third transistor,
the second terminal of the third transistor is coupled to the third terminal of the fourth transistor,
the first terminal of the third transistor is coupled to a first bias voltage,
the first terminal of the fourth transistor is coupled to a first terminal of the two-terminal passive network and a second terminal of the two-terminal passive network is coupled to a second bias voltage,
the first terminal of the fourth transistor is not coupled to a grounding capacitor, and
at a target frequency, an impedance of the two-terminal passive network is such that a voltage swing at the first terminal of the fourth transistor is substantially equal to half of a voltage swing at an output of the current mirror arrangement.

2. The electronic device according to claim 1 , wherein the first bias voltage and the second bias voltage are such that a quiescent voltage between the first and the second terminals of the third transistor is substantially equal to a quiescent voltage between the first and the second terminals of the fourth transistor.

3. The electronic device according to claim 1 , wherein the current mirror arrangement includes M stages, where:
M is an integer greater than 1,
each stage i of the M stages includes a respective set of a transistor and a two-terminal passive network, where i is an integer between 1 and M,
for i=1, the transistor of the stage i is the fourth transistor and the two-terminal passive network of the stage i is the two-terminal passive network, and
for i>1:
the first terminal of the transistor of the stage i is coupled to the first terminal of the two-terminal passive network of the stage i,
the second terminal of the two-terminal passive network of the stage i is coupled to a bias voltage i of the stage i, and
the third terminal of the transistor of the stage i is coupled to the second terminal of the transistor of the stage i−1.

4. The electronic device according to claim 3 , wherein:
for i<M, the second terminal of the transistor of the stage i is coupled to the third terminal of the transistor of the stage i+1, and
the second terminal of the transistor of the stage M is coupled to an output of the current mirror arrangement.

5. The electronic device according to claim 3 , wherein, for any i between 1 and M, an impedance of the two-terminal passive network of the stage i is such that a voltage swing at the first terminal of the transistor of the stage i is substantially equal to i×VO/(M+1), where VO is a voltage swing at an output of the current mirror arrangement.

6. The electronic device according to claim 1 , wherein, for each of the first, second, third, and fourth transistors, the first terminal is a base terminal, the second terminal is a collector terminal, and the third terminal is an emitter terminal.

7. The electronic device according to claim 6 , wherein an emitter area of at least one of the second, third, and fourth transistors is K times of an emitter area of the first transistor, where K is a positive number.

8. The electronic device according to claim 1 , wherein, for each of the first, second, third, and fourth transistors, the first terminal is a gate terminal, the second terminal is a drain terminal, and the third terminal is a source terminal.

9. The electronic device according to claim 8 , wherein an aspect ratio of at least one of the second, third, and fourth transistors is K times of an aspect ratio of the first transistor, where K is a positive number.

10. The electronic device according to claim 1 , wherein:
the second terminal of the first transistor is coupled to the input of the current mirror circuit, and
the second terminal of the second transistor is coupled to the output of the current mirror circuit.

11. The electronic device according to claim 1 , wherein the target frequency is a frequency of a signal at the second terminal of the fourth transistor.

12. The electronic device according to claim 1 , wherein the electronic device is a system that includes an analog-to-digital converter (ADC) and a driver for the ADC, and wherein the current mirror arrangement is a part of the driver for the ADC.

13. The electronic device according to claim 1 , wherein the electronic device is a driver for an analog-to-digital converter.

14. A electronic device, comprising a current mirror arrangement, the current mirror arrangenment including:
a current mirror circuit, comprising a first transistor at an input of the current mirror circuit and a second transistor at an output of the current mirror circuit;
a third transistor;
a fourth transistor; and
a two-terminal passive network,
wherein:
the second transistor is in a common-emitter configuration,
each of the third transistor and the fourth transistor is in a common-base configuration,
an output of the second transistor is coupled to an input of the third transistor,
an output of the third transistor is coupled to an input of the fourth transistor,
an output of the fourth transistor is coupled to an output of the current mirror arrangement,
a base terminal of the third transistor is coupled to a first bias voltage,
a base terminal of the fourth transistor is coupled to a first terminal of the two-terminal passive network and is not coupled to a capacitor that is coupled to a ground potential,
a second terminal of the two-terminal passive network is coupled to a second bias voltage, and
an impedance of the two-terminal passive network is such that a voltage swing at the base terminal of the fourth transistor is substantially equal to half of a voltage swing at the output of the fourth transistor.

15. The electronic device according to claim 14 , wherein the first bias voltage and the second bias voltage are such that a quiescent voltage between the base terminal and the output of the third transistor is substantially equal to a quiescent voltage between the base terminal and the output of the fourth transistor.

16. The electronic device according to claim 14 , wherein the two-terminal passive network includes one or more resistors, capacitors, and inductors.

17. The electronic device according to claim 14 , wherein an impedance of the two-terminal passive network is such that a voltage swing at the base terminal of the fourth transistor is substantially equal to half of a voltage swing at an output of the current mirror arrangement.

18. The electronic device according to claim 14 , wherein the electronic device is a system that includes an analog-to-digital converter (ADC) and a driver for the ADC, and wherein the current mirror arrangement is a part of the driver for the ADC.

19. The electronic device according to claim 14 , wherein the electronic device is a driver for an analog-to-digital converter.

20. An electronic devic

Assignees

• Analog Devices Inc

Inventors

• Aksin Devrim
• Foroudi Omid

Classifications

• H03F2200/555

  A voltage generating circuit being realised for biasing different circuit elements · CPC title

• G05F3/262

  using field-effect transistors only · CPC title

• H03F3/345

  with field-effect devices (H03F3/347 takes precedence) · CPC title

• H03F1/42

  Modifications of amplifiers to extend the bandwidth · CPC title

• G05F3/265 Primary

  using bipolar transistors only · CPC title