Analog-to-digital converter and method to operate an analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-11258455-B2
Application number	US-201917052461-A
Country	US
Kind code	B2
Filing date	Apr 29, 2019
Priority date	May 3, 2018
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

An analog-to-digital converter (ADC) is based on single-bit delta-sigma quantization. The ADC includes an integrator, a threshold detector, a feedback block, a range control circuit and an output processing block. The ADC is configured to, based on its own generated digital bitstream, adjust the magnitude of a subtrahend signal in order to achieve autonomous auto-ranging of the ADC during the integration time of a measurement. In particular, the auto-ranging allows for the efficient conversion of an analog input signal with high dynamic range, for example ambient light, to a digital output signal.

First claim

We claim:

1. An analog-to-digital converter, ADC, based on single-bit delta-sigma quantization configured to convert an analog input signal to a digital output signal, the ADC comprising
an integrator configured to generate an integrated signal by means of an integration of a difference of the input signal and a subtrahend signal;
a threshold detector configured to generate discrete bit signals of a bitstream, the bit signals indicating whether the integration signal is smaller or larger than a first threshold value;
a feedback block configured to generate the subtrahend signal based on the bit signals;
a range control circuit configured to adjust based on the bitstream a magnitude of the subtrahend signal corresponding to a range value using a factor of a set of fixed factors and to provide for each of the discrete bit signals an associated range value to an output processing block; and
the output processing block, configured to generate the digital output signal from the bitstream and from the associated range value for each of the discrete bit signals of the bitstream.

2. The ADC according to claim 1 , wherein the bitstream is generated within a predefined measurement time and the discrete bit signals of the bitstream are generated at a predefined clock rate.

3. The ADC according to claim 1 , wherein the generation of the digital output signal comprises multiplying each of the discrete bit signals of the bitstream with a factor corresponding to the associated range value.

4. The ADC according to claim 1 , wherein the range control circuit is further configured to adjust the range value using a factor of a set of powers of 2.

5. The ADC according to claim 1 , wherein
the analog input signal is bipolar; and
the range control circuit is further configured to
increase the range value if a sequence of the bitstream comprises a number of consecutive high values and/or a number of consecutive low values; and
to decrease the range value if the sequence comprises a number of consecutive alternating low and high values and/or a number of consecutive alternating high and low values.

6. The ADC according to claim 5 , wherein the range control circuit is further configured to set a polarity of the subtrahend signal based on the bitstream.

7. The ADC according to claim 1 , wherein
the analog input signal is unipolar; and
the range control circuit is further configured to
increase the range value if a sequence of the bitstream comprises a number of consecutive high values; and
to decrease the range value if the sequence comprises a number of consecutive low values.

8. The ADC according to claim 1 , wherein the range control circuit is further configured to predetermine an initial value for the range value.

9. The ADC according to claim 1 , wherein the range control circuit is further configured to increase and decrease the range value in a different manner.

10. The ADC according to claim 1 , wherein the integrator comprises a non-linear capacitor.

11. The ADC according to claim 1 , wherein
the ADC further comprises a second threshold detector configured to generate discrete second bit signals of a second bitstream, the second bit signals indicating whether the integration signal is smaller or larger than a second threshold value; and
the range control circuit is further configured to adjust the range value based on the second bitstream.

12. A sensor arrangement comprising a photodiode and an analog-to digital converter, ADC, based on single-bit delta-sigma quantization according to claim 1 , wherein the ADC is configured to convert an analog signal based on a photo current of the photodiode to a digital signal.

13. A method for operating an analog-to-digital converter, ADC, based on single-bit delta-sigma quantization, the method comprising
generating an integrated signal by means of an integration of a difference of an analog input signal and a subtrahend signal;
generating discrete bit signals of a bitstream based on comparisons between the integrated signal and a first threshold value;
generating the subtrahend signal based on the bit signals;
adjusting based on the bitstream a magnitude of the subtrahend signal corresponding to a range value using a factor of a set of fixed factors;
assigning each of the discrete bit signals an associated range value; and
generating a digital output signal from the bitstream and from the associated range value for each of the discrete bit signals of the bitstream.

14. The method according to claim 13 , further comprising an increase and decrease of the range value based on the bitstream using a factor of a set of fixed factors.

15. The method according to claim 13 , wherein the increase and decrease of the range value is performed in a different manner.

16. The method according to claim 13 , further comprising an increase and decrease of the range value based on the bitstream using a factor of a set of powers of 2.

Assignees

• Ams Ag

Inventors

• Theiler Helmut
• Lenhard Herbert

Classifications

• H03M3/484 Primary

  by adapting the gain of the feedback signal, e.g. by adapting the reference values of the digital/analogue converter in the feedback path · CPC title

• H03M3/49

  in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values · CPC title

• H03M3/43

  the quantiser being a single bit one · CPC title