Techniques for addressing phase noise and phase lock loop performance

Patent metadata

Field	Value
Publication number	US-11258450-B2
Application number	US-201816766921-A
Country	US
Kind code	B2
Filing date	Mar 30, 2018
Priority date	Mar 30, 2018
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.

First claim

What is claimed is:

1. A circuit for cancelling phase noise, the circuit comprising:
a first mixer configured to receive a modulated signal;
a digital phase-lock loop (DPLL) configured to provide a first clock signal to the first mixer and to provide a phase noise estimate of phase noise of the DPLL;
an analog-to-digital converter (ADC) configured to receive an output of the first mixer and provide digital information of the modulated signal; and
an equalization circuit configured to receive the phase noise estimate from the DPLL and to apply a digital representation of the phase noise of the DPLL to the digital information via a second mixer to reduce phase noise of digital information,
wherein the DPLL comprises a time-to-digital converter (TDC) in a feedback path of the DPLL, the TDC configured to receive the first clock signal and a reference clock signal and generate a digital representation of a phase difference between the first clock signal and the reference clock signal, and
wherein the phase noise estimate is generated by the DPLL based on a comparison of the digital representation of the phase difference with a predetermined phase difference and parameters of the first clock signal are adjusted based on the phase noise estimate.

2. The circuit of claim 1 , wherein the equalization circuit includes a resample circuit configured to sample the phase noise estimate at a rate corresponding to a rate of the ADC to compensate for the phase noise, the phase noise comprising a random, non-deterministic component of phase error.

3. The circuit of claim 1 , wherein the TDC is configured to receive the first clock signal, to compare a phase of the first clock signal to a phase of the reference clock signal, and to generate the digital representation of the phase difference between the first clock signal and the reference clock signal based on the comparison, and
wherein the DPLL comprises:
a digitally controlled oscillator (DCO) configured to provide the first clock signal;
a digital phase detector in the feedback path configured to compare the digital representation of the phase difference with a predetermined phase difference to generate the phase noise estimate; and
a digital loop filter configured to receive the phase noise estimate for use in adjusting parameters of the DCO, and
wherein the resample circuit is configured to sample the phase noise estimate from the digital phase detector at a rate corresponding to a rate of the ADC.

4. The circuit of claim 1 , wherein the first mixer is an analog mixer.

5. The circuit of claim 1 , wherein the second mixer is a digital mixer.

6. A circuit for cancelling phase noise, the circuit comprising:
a first mixer configured to receive a modulated signal;
a digital phase-lock loop (DPLL) configured to provide a first clock signal to the first mixer and to provide a phase noise estimate of phase noise of the DPLL;
an analog-to-digital converter (ADC) configured to receive an output of an analog mixer and provide digital information of the modulated signal;
an equalization circuit configured to receive the phase noise estimate from the DPLL and to apply a digital representation of the phase noise of the DPLL to the digital information via a second mixer to reduce phase noise of digital information,
wherein the equalization circuit includes a resample circuit configured to sample the phase noise estimate from a digital phase detector of the DPLL at a rate corresponding to a rate of the ADC, and
wherein the DPLL includes:
a digitally controlled oscillator (DCO) configured to provide the first clock signal;
the time-to-digital converter (TDC) configured to receive the first clock signal, to compare a phase of the first clock signal to a phase of a reference clock signal, and to generate digital representation of a phase difference between the first clock signal and the reference clock signal;
a digital phase detector configured to compare the digital representation of the phase difference with a programmed phase difference and to provide an phase error signal based on the comparison of the digital representation of the phase with the programmed phase difference; and
a digital loop filter configured to receive the error signal and adjust parameters of the DCO.

7. A circuit for cancelling phase noise, the circuit comprising:
a first mixer configured to receive a modulated signal;
a digital phase-lock loop (DPLL) configured to provide a first clock signal to the first mixer and to provide a phase noise estimate of phase noise of the DPLL;
an analog-to-digital converter (ADC) configured to receive an output of the first mixer and provide digital information of the modulated signal;
an equalization circuit configured to receive the phase noise estimate from the DPLL and to apply a digital representation of the phase noise of the DPLL to the digital information via a second mixer to reduce phase noise of digital information,
wherein the equalization circuit includes a resample circuit configured to sample the phase noise estimate from a digital phase detector of the DPLL at a rate corresponding to a rate of the ADC, and
wherein the equalization circuit includes an adaptive filter configured to conform a shape of the digital representation of the phase noise of the DPLL at the second mixer to a shape of the phase noise of the DPLL at the first mixer.

8. A circuit for cancelling phase noise, the circuit comprising:
a first mixer configured to receive a modulated signal;
a digital phase-lock loop (DPLL) configured to provide a first clock signal to the first mixer and to provide a phase noise estimate of phase noise of the DPLL;
an analog-to-digital converter (ADC) configured to receive an output of the first mixer and provide digital information of the modulated signal;
an equalization circuit configured to receive the phase noise estimate from the DPLL and to apply a digital representation of the phase noise of the DPLL to the digital information via a second mixer to reduce phase noise of digital information; and,
a second DPLL configured to provide a second clock signal to the ADC, wherein the second DPLL is different from the DPLL.

9. The circuit of claim 8 , including a second compensation circuit configured to receive phase error information from the second DPLL and to apply a second phase compensation signal to the digital information via a third mixer to reduce phase noise from the second DPLL in the digital information.

10. The circuit of claim 9 , wherein the third mixer is a digital mixer.

11. A method of compensating for phase noise, the phase noise comprising a random, non-deterministic component of phase error, the method comprising:
receiving a modulated signal at an analog mixer;
receiving a clock signal at the analog mixer;
converting an analog output of the analog mixer to a digital signal;
digitally estimating phase noise of the clock signal to provide a digital estimate of the phase noise of the clock signal; and
applying the digital estimate of the phase noise to the digital signal using a digital mixer to reduce phase noise in the digital signal,
wherein receiving a clock signal at the analog mixer includes generating a clock signal using a digital phase lock loop (DPLL), and
wherein generating the clock signal includes generating an estimate of the phase noise of the clock signal at a time-to-digital converter (TDC) of the DPLL,
wherein the TDC configured to receive the first clock signal and a reference clock signal and generate a digital representation of a phase difference between the clock signal and the reference clock signal,
wherein the phase noise estimate is generated by the DPLL based on

Assignees

• Intel Corp

Inventors

• Karandikar Niranjan
• Ballantyne Wayne
• Chance Gregory
• Hughes Simon
• Schwartz Daniel
• Tanzi Nebil

Classifications

• H03L7/0805 Primary

  the loop being adapted to provide an additional control signal for use outside the loop · CPC title

• H03L7/185

  using a mixer in the loop (H03L7/187 - H03L7/195 take precedence) · CPC title

• H03L7/0992 Primary

  comprising a counter or a frequency divider · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title