Compact offset drift trim implementation

Patent metadata

Field	Value
Publication number	US-11258414-B2
Application number	US-202016803514-A
Country	US
Kind code	B2
Filing date	Feb 27, 2020
Priority date	Feb 27, 2020
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

Disclosed embodiments include a method for reducing amplifier offset drift comprised of receiving a first differential input signal at a first transistor base terminal and a second differential input signal at a second transistor base terminal, coupling the collector of the first transistor to the emitter of a third transistor and the emitter of the second transistor to the emitter of a fourth transistor, then coupling the base of the third transistor to the base of the fourth transistor. The method is also comprised of coupling the collector of the fourth transistor to an output terminal, generating a temperature dependent error correction current to minimize the difference in the amount of current flowing through the third transistor and the amount of current flowing through the fourth transistor, then injecting the error correction current into the emitter terminal of at least one of either the third transistor or the fourth transistor.

First claim

What is claimed is:

1. A method for reducing offset drift in an amplifier comprised of:
receiving a first differential input signal at the control terminal of a first transistor and a second differential input signal at the control terminal of a second transistor;
coupling a first terminal of the first transistor to a second terminal of a third transistor and a first terminal of the second transistor to a second terminal of a fourth transistor;
coupling a control terminal of the third transistor to a control terminal of the fourth transistor;
coupling a first terminal of the fourth transistor to an output terminal;
generating a temperature dependent error correction current to minimize the difference in the amount of current flowing through the third transistor and the amount of current flowing through the fourth transistor; and
providing the error correction current to the second terminal of at least one of the third transistor or the fourth transistor.

2. The method of claim 1 , wherein the error correction current has an approximately opposite response to a change in temperature compared to a temperature dependent offset error in the amplifier.

3. The method of claim 1 , wherein a switch controls whether the polarity of the error correction current is positive or negative.

4. The method of claim 3 , wherein the switch can prevent the error correction current from being injected into the third transistor or fourth transistor.

5. The method of claim 1 , wherein the error correction current is first generated as an error correction voltage, and the error correction voltage is then input to a transconductance stage that converts the voltage to a current.

6. The method of claim 1 , wherein a current source is coupled to a second terminal of the first transistor and a second terminal of the second transistor, raising the voltage at the second terminal of the first transistor and the second terminal of the second transistor above a lower supply voltage.

7. The method of claim 1 , wherein a control terminal is a base, a first terminal is a collector, and a second terminal is an emitter.

8. A circuit comprising:
a first transistor having a control terminal, a first terminal, and a second terminal, the control terminal is coupled to a first differential input terminal, and the second terminal is coupled to a first terminal of an error correction circuit;
a second transistor having a control terminal, a first terminal, and a second terminal, the control terminal is coupled to a second differential input terminal, the first terminal is coupled to the first terminal of the first transistor, and the second terminal is coupled to a second terminal of the error correction circuit;
a third transistor having a control terminal, a first terminal, and a second terminal, the first terminal is coupled to the first terminal of the error correction circuit;
a fourth transistor having a control terminal, a first terminal, and a second terminal, the control terminal is coupled to the control terminal of the third transistor, and the first terminal is coupled to the second terminal of the error correction circuit; and
an output amplifier stage with an input coupled to the second terminal of the fourth transistor and an output coupled to an output terminal.

9. The circuit of claim 8 , wherein the error correction circuit minimizes the difference between the current through the third transistor and the current through the fourth transistor.

10. The circuit of claim 8 , wherein the error correction circuit includes a switch that determines whether the current output has a positive polarity or a negative polarity.

11. The circuit of claim 10 , wherein the switch can decouple the error correction circuit from the third transistor and the fourth transistor.

12. The circuit of claim 8 , further comprising a current mirror coupled between the second terminal of the third transistor and a first voltage source, and between the second terminal of the fourth transistor and the first voltage source.

13. The circuit of claim 12 , wherein the control terminal is a base of a transistor, the first terminal is an emitter of a transistor, and the second terminal is a collector of a transistor.

14. The circuit of claim 8 , wherein the circuit includes a current source coupled to the first terminal of the first transistor and the first terminal of the second transistor.

15. An error correction circuit comprising:
a first transistor having a control terminal, a first terminal, and a second terminal, the second terminal is coupled to a current source through a first resistor, and the control terminal is coupled to a first differential voltage output and to the first terminal through a second resistor and a third resistor;
a second transistor having a control terminal, a first terminal, and a second terminal, the second terminal is coupled to the current source through a fourth resistor, and the control terminal is coupled to a second differential voltage output through a fifth resistor and to the first terminal through the fifth resistor and a sixth resistor;
a transconductance stage having a differential input coupled to the first differential voltage output and the second differential voltage output, and a differential output coupled to a first differential current output and a second differential current output; and
a polarity selection switch coupled to the first differential current output and the second differential current output, and having a differential error correction current output.

16. The error correction circuit of claim 15 , wherein the polarity selection switch determines whether the polarity of the differential error correction current output is positive or negative.

17. The error correction circuit of claim 16 , wherein the polarity selection switch can disable the differential error correction current output.

18. The error correction circuit of claim 15 , wherein the transconductance stage includes a third transistor and a fourth transistor.

19. The error correction circuit of claim 18 , wherein the third transistor and the fourth transistor are between a current source and the differential output of the transconductance stage.

20. The error correction circuit of claim 15 , wherein there is at least one temperature where differential voltage across the first differential voltage output and the second differential voltage output is approximately zero.

Assignees

• Texas Instruments Inc

Inventors

• Schaffer Viola

Classifications

• H03F2203/45674

  the LC comprising one current mirror · CPC title

• H03F2200/447

  the amplifier being protected to temperature influence · CPC title

• H03F3/45085

  Long tailed pairs (H03F3/45112, H03F3/45139 take precedence) · CPC title

• H03F2203/45212

  the differential amplifier being designed to have a reduced offset · CPC title

• H03F2200/456

  A scaled replica of a transistor being present in an amplifier · CPC title