Stacked, high-blocking InGaAs semiconductor power diode

Patent metadata

Field	Value
Publication number	US-11257909-B2
Application number	US-202016863483-A
Country	US
Kind code	B2
Filing date	Apr 30, 2020
Priority date	Apr 30, 2019
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

First claim

What is claimed is:

1. A stacked, high-blocking InGaAs semiconductor power diode comprising:
a first metallic terminal contact layer formed at least in regions;
a highly doped semiconductor contact region of a first conductivity type, having a dopant concentration greater than 1×1018 N/cm3 and having a first lattice constant;
a drift layer of a second conductivity type, having the first lattice constant and having a layer thickness greater than 10 um;
a semiconductor contact layer of the second conductivity type, including an upper side and an underside, and having a dopant concentration greater than 5×1017 N/cm3 and a layer thickness of more than 0.5 um and less than 850 um;
a second metallic terminal contact layer,
wherein the first metallic terminal contact layer is formed above the highly doped semiconductor contact region, the highly doped semiconductor contact region is formed above the drift layer, the drift layer is formed above the semiconductor contact layer, and the semiconductor contact layer is formed above the second metallic terminal contact layer,
wherein the second metallic terminal contact layer is integrally connected to the underside of the semiconductor contact layer,
wherein the semiconductor contact layer has a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP,
wherein the drift layer and the highly doped semiconductor contact region each comprise an InGaAs compound or consist substantially of InGaAs,
wherein the first lattice constant is higher than the lattice constant of GaAs, and
wherein the highly doped semiconductor contact region is directly adjacent to the drift layer, or
wherein the highly doped semiconductor contact region is separated from the drift layer by a doped intermediate layer (, which is a single layer of first conductivity type), the doped intermediate layer being directly adjacent to the drift layer and the highly doped semiconductor contact region being directly adjacent to the doped intermediate layer,
wherein the doped intermediate layer is a single layer of the first conductivity type.

2. The stacked, high-blocking InGaAs semiconductor power diode according to claim 1 , wherein the highly doped semiconductor contact region is spaced a distance apart from the drift layer by the doped intermediate layer of the first conductivity type and having a dopant concentration of less than 5×10 15 N/cm 3 and having the first lattice constant and a thickness between 1 um and 30 um, and wherein the doped intermediate layer comprises an InGaAs compound or consists substantially of InGaAs.

3. The stacked, high-blocking InGaAs semiconductor power diode according to claim 1 , wherein the first lattice constant and the second lattice constant are equal in size, and the semiconductor contact layer comprises InP or consists substantially of InP.

4. The stacked, high-blocking InGaAs semiconductor power diode according to claim 1 , wherein a highly doped metamorphic buffer layer sequence is formed between the drift layer and the second metallic terminal contact layer, and wherein the metamorphic buffer layer sequence has a dopant concentration greater than 5·10 17 N/cm 3 or greater than 1·10 17 N/cm 3 or greater than 5·10 16 N/cm 3 or greater than 2·10 16 N/cm 3 and a layer thickness of more than 0.5 μm and less than 20 μm, and which is of the first conductivity type or the second conductivity type, and wherein the metamorphic buffer layer sequence includes an upper side having the first lattice constant and an underside having the second lattice constant, the upper side being arranged in the direction of the drift layer, and the first lattice constant being higher than or lower than the second lattice constant.

5. The stacked, high-blocking InGaAs semiconductor power diode according to claim 4 , wherein the semiconductor contact layer comprises the metamorphic buffer layer or consists substantially of the metamorphic buffer layer.

6. The stacked, high-blocking InGaAs semiconductor power diode according to claim 1 , wherein the first conductivity type is p and the second conductivity type is n, or the first conductivity type is n and the second conductivity type is p.

7. The stacked, high-blocking InGaAs semiconductor power diode according to claim 1 , wherein the highly doped semiconductor contact region is a planar layer or has a trough-shaped design.

8. The stacked, high-blocking InGaAs semiconductor power diode according to claim 1 , wherein the highly doped semiconductor contact region, the drift layer, and the semiconductor layers contact layer have a monolithic design.

9. The stacked, high-blocking InGaAs semiconductor power diode according to claim 1 , wherein a substrate layer of the first conductivity type or of the second conductivity type is formed between the drift layer and the second metallic terminal contact layer, and the substrate layer comprises InP or is made up of InP.

10. The stacked, high-blocking InGaAs semiconductor power diode according to claim 9 , wherein the semiconductor contact layer comprises the substrate layer or consists substantially of the substrate layer.

11. The stacked, high-blocking InGaAs semiconductor power diode according to claim 1 , wherein a substrate layer of the first conductivity type or of the second conductivity type is formed between the drift layer and the second metallic terminal contact layer, and the substrate layer comprises a layer sequence of InP and GaAs or consists substantially of the layer sequence of InP and GaAs.

12. The stacked, high-blocking InGaAs semiconductor power diode according to claim 1 , wherein a breakdown voltage of the power diode is over 200 V.

Assignees

• Azur Space Solar Power Gmbh
• 3 5 Power Electronics Gmbh

Inventors

• Fuhrmann Daniel
• Keller Gregor
• WAECHTER Clemens
• Dudek Volker

Classifications

• H10D8/00 Primary

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D62/852

  being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D8/411

  PN diodes having planar bodies · CPC title