Semiconductor device

Patent metadata

Field	Value
Publication number	US-11257754-B2
Application number	US-201916550189-A
Country	US
Kind code	B2
Filing date	Aug 24, 2019
Priority date	Jan 8, 2019
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

A semiconductor device includes a substrate having a first region, a second region, a first buffer region, and a second buffer region. A plurality of conductive lines is disposed on the first region of the substrate. An inductor is disposed on the second region of the substrate, and a dummy pattern is disposed on the first buffer region of the substrate. The first buffer region is provided between the first region and the second region. The second buffer region is provided between the first buffer region and the second region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having a first region, a second region, a first buffer region, and a second buffer region;
a plurality of conductive lines on the first region of the substrate;
an inductor on the second region of the substrate;
a dummy pattern on the first buffer region of the substrate; and
a solder ball provided on at least one of the plurality of conductive lines in the first region of the substrate and spaced apart from the second region, the first buffer region, and the second buffer region of the substrate, wherein:
the first buffer region is provided between the first region and the second region,
the second buffer region is provided between the first buffer region and the second region,
the inductor includes a conductor having a first inner surface and a second inner surface facing each other,
the dummy pattern is not provided between the first inner surface and the second inner surface of the conductor,
the dummy pattern is not provided on the second region of the substrate,
no conductive component is disposed between the dummy pattern and the inductor,
when viewed in plan, a first minimum distance between the dummy pattern and the conductive lines is less than a second minimum distance between the dummy pattern and the inductor,
the first buffer region has a width of about 15 μm to about 30 μm, and
the first minimum distance is less than the width of the first buffer region.

2. The semiconductor device of claim 1 , wherein the dummy pattern is not provided on the second buffer region of the substrate.

3. The semiconductor device of claim 1 , further comprising:
a plurality of transistors on the first region of the substrate, wherein
the conductive lines are electrically connected to the transistors.

4. The semiconductor device of claim 1 , further comprising:
an interlayer dielectric layer on the substrate and having a first top surface and a second top surface connected to each other, wherein:
the conductive lines are disposed on the first top surface of the interlayer dielectric layer,
the conductor disposed on the second top surface of the interlayer dielectric layer, and
the second top surface of the interlayer dielectric layer is located at a different level from that of the first top surface of the interlayer dielectric layer.

5. The semiconductor device of claim 4 , wherein top surfaces of the conductive lines are located at a lower level than that of a top surface of the conductor.

6. The semiconductor device of claim 5 , wherein a level difference between a top surface of the dummy pattern and the top surfaces of the conductive lines is less than a level difference between the top surface of the conductor and the top surface of the dummy pattern.

7. The semiconductor device of claim 4 , wherein the dummy pattern is not provided on or in the interlayer dielectric layer on the second region of the substrate.

8. A semiconductor device comprising:
a substrate having a first region, a second region, and a buffer region between the first region and the second region;
a plurality of internal components on the first region of the substrate;
a plurality of conductive lines on the first region of the substrate and electrically connected to the internal components;
an inductor on the second region of the substrate; and
a dummy pattern on the buffer region of the substrate, wherein:
the inductor includes a conductor having a first inner surface and a second inner surface facing each other,
the dummy pattern is not provided between the first inner surface and the second inner surface of the conductor,
when viewed in plan, a first minimum distance between the dummy pattern and the conductive lines is less than a second minimum distance between the dummy pattern and the inductor,
the buffer region has a width of about 15 μm to about 30 μm, and
the first minimum distance is less than the width of the buffer region.

9. The semiconductor device of claim 8 , further comprising:
an interlayer dielectric layer on the substrate and having a first top surface and a second top surface connected to each other, wherein:
the conductive lines are disposed on the first top surface of the interlayer dielectric layer,
wherein the conductor is on the second top surface of the interlayer dielectric layer, and
the first top surface of the interlayer dielectric layer is provided at a lower level than that of the second top surface.

10. The semiconductor device of claim 8 , wherein the plurality of internal components are transistors.

11. The semiconductor device of claim 8 , wherein the plurality of internal components are memory transistors.

12. A semiconductor device having a first region, a second region mutually exclusive with the first region, a buffer region, and a dummy region between the first region and the second region, the semiconductor device comprising:
a substrate;
a first dielectric layer disposed over the substrate in each of the first region, the dummy region, and the second region;
a second dielectric layer disposed over the first dielectric layer in each of the first region, the dummy region, and the second region;
a conductive line formed within the first dielectric layer and electrically connected to a first electronic device;
an inductor formed within the second dielectric layer; and
a dummy pattern, formed in the first dielectric layer, that is not electrically connected to an electronic device, wherein:
the buffer region is provided between the first region and the second region,
the conductive line is disposed in the first region, but not in the second region and the dummy region,
the dummy pattern is disposed in the dummy region, but not in the first region and the second region,
the inductor is disposed in the second region but not the first region and the dummy region,
the inductor includes a conductor having a first inner surface and a second inner surface facing each other,
the dummy pattern is not provided between the first inner surface and the second inner surface of the conductor,
the dummy pattern is disposed between the conductive line and the inductor, from a perspective of a plan view,
when viewed in plan, a first minimum distance between the dummy pattern and the conductive line is less than a second minimum distance between the dummy pattern and the inductor,
the buffer region has a width of about 15 μm to about 30 μm, and
the first minimum distance is less than the width of the buffer region.

13. The semiconductor device of claim 12 , wherein the first electronic device is a transistor.

14. The semiconductor device of claim 12 , wherein the first electronic device is a memory transistor.

15. The semiconductor device of claim 12 , wherein a first height above the substrate of a top surface of the first dielectric layer disposed immediately adjacent to the conductive line differs from a second height above the substrate of a top surface of the first dielectric layer disposed immediately adjacent to the dummy pattern.

16. The semiconductor device of claim 12 , wherein a first height above the substrate of a top surface of the second dielectric layer disposed closest to the conductive line differs from a second height above the substrate of a top surface of the second dielectric layer disposed closest to the dummy pattern.

17. The semiconductor device of claim 16 , wherein a third height above the substrate of a top surface of the second dielectric layer disposed immediately adjacent to the inductor differs from the second heigh

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Joon-Nyung
• Ahn Jeong Hoon

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/497 Primary

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D84/00 Primary

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H01L23/5227 Primary

  Electricity · mapped topic