Phase lock circuitry using frequency detection

Patent metadata

Field	Value
Publication number	US-11251796-B2
Application number	US-202017099114-A
Country	US
Kind code	B2
Filing date	Nov 16, 2020
Priority date	Mar 28, 2019
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

First claim

What is claimed is:

1. A frequency detector comprising:
a delay circuit configured to receive a first signal and a second signal and to apply a delay to the first signal to provide a delayed first signal;
a first frequency detection circuit configured to receive the delayed first signal and provide a pulse on a first output signal in response to detection that the delayed first signal has a frequency that is greater than a frequency of the second signal; and
a second frequency detection circuit configured to receive the second signal and to provide a pulse on a second output signal in response to detection that the second signal has a frequency that is greater than a frequency of the delayed first signal.

2. The frequency detector of claim 1 , wherein the delay circuit comprises a pair of serially-coupled inverters configured to receive the first signal and to provide the delayed first signal.

3. The frequency detector of claim 1 , wherein the delay circuit is configured to apply the delay to the first signal during a first time period and to apply the delay to the second signal during a second time period to provide a delayed second signal, wherein, during the second time period, the first signal is provided to the first frequency detection circuit and the delayed second signal is provided to the second frequency detection circuit.

4. The frequency detector of claim 1 , wherein the delay circuit comprises a multiplexer configured to selectively provide the first signal or the delayed first signal based on a value of a control signal.

5. The frequency detector of claim 1 , wherein the first frequency detection circuit comprises:
a first flip-flop configured to propagate a first logical signal to an output in response to the delayed first signal; and
a second flip-flop configured to propagate an output of the first flip-flop to an output in response to the delayed first signal.

6. The frequency detector of claim 5 , further comprising a reset circuit configured to reset the first and second frequency detection circuits based on relative timing of the delayed first signal and the second signal.

7. The frequency detector of claim 6 , wherein the reset circuit includes an AND gate coupled in series with a pair of inverters, wherein the AND gate is configured to compare the first logical signal with a signal from the second frequency detection circuit to determine whether to reset the first and second frequency detection circuits.

8. The frequency detector of claim 5 , wherein the second frequency detection circuit comprises:
a third flip-flop configured to propagate a second logical signal to an output in response to the second signal; and
a fourth flip-flop configured to propagate an output of the third flip-flop to an output in response to the second signal.

9. The frequency detector of claim 5 , wherein the first frequency detection circuit further comprises a third flip-flop configured to propagate a third logical signal to an output in response to the delayed first signal.

10. The frequency detector of claim 1 , wherein the delay circuit is configured to apply an asynchronous delay to the first signal.

11. A method comprising:
receiving a first signal and a second signal at a frequency detector;
during a first time period:
delaying the first signal to provide a delayed first signal; and
comparing a frequency of the delayed first signal and the second signal to detect a frequency deviation between the first signal and the second signal; and

in response to detection of a frequency deviation, causing a frequency of one of the first or second signals to change; and
during a second time period after the first time period:
delaying the second signal to provide a delayed second signal; and
comparing a frequency of the delayed second signal and a frequency of the first signal to detect a frequency deviation between the first signal and the second signal, wherein a duration of the first time period and the second time period is based on a count of cycles of the first signal or the second signal.

12. A method comprising:
receiving a first signal and a second signal at a frequency detector;
during a first time period:
delaying the first signal to provide a delayed first signal; and
comparing a frequency of the delayed first signal and the second signal to detect a frequency deviation between the first signal and the second signal; and

in response to detection of a frequency deviation, causing a frequency of one of the first or second signals to change;
during a second time period after the first time period:
delaying the second signal to provide a delayed second signal; and
comparing a frequency of the delayed second signal and a frequency of the first signal to detect a frequency deviation between the first signal and the second signal; and

during a third time period after the second time period:
delaying the first signal to provide the delayed second signal; and
comparing the frequency of the delayed first signal and the frequency of the second signal to detect a frequency deviation between the first signal and the second signal.

13. The method of claim 11 , further comprising delaying the first signal via a pair of inverters.

14. The method of claim 11 , further comprising adjusting a frequency of a clock signal based on the frequency deviation.

15. The method of claim 11 , further comprising receiving the second signal from a voltage-controlled oscillator.

16. The method of claim 11 , further comprising resetting the comparison between the frequency of the delayed first signal and the frequency of the second signal based on relative timing differences between the delayed first signal and the second signal.

17. The method of claim 11 , further comprising delaying the first signal via an asynchronous delay.

18. The method of claim 11 , further comprising determining a phase difference between the first signal and the second signal.

Assignees

• Micron Technology Inc

Inventors

• Takai Yasuhiro
• Kuzmenka Maksim
• Balakrishnan Mani
• Brox Martin

Classifications

• H03L7/087 Primary

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03K5/14

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• G11C2207/107

  Serial-parallel conversion of data or prefetch · CPC title

• G11C7/1093

  Input synchronization · CPC title