CMOS image sensor with pump gate and extremely high conversion gain

Patent metadata

Field	Value
Publication number	US-11251215-B2
Application number	US-201916397841-A
Country	US
Kind code	B2
Filing date	Apr 29, 2019
Priority date	Apr 1, 2014
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

Some embodiments relate to an image sensor pixel comprising a transfer gate formed on a first surface of a semiconductor substrate, a floating diffusion formed in the first surface of the semiconductor substrate, and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially beneath the transfer gate. The transfer gate is spaced away from the floating diffusion such that an intervening semiconductor region provides a potential barrier to charge flow from beneath the transfer gate to the floating diffusion. The transfer gate is operable to control a vertical pump gate to selectively transfer charge from the charge accumulation/storage region to the floating diffusion by pumping charge from the buried charge accumulation/storage region underlying the transfer gate, over the potential barrier, and out to the floating diffusion, such that full charge transfer can be achieved without overlapping the edge of the transfer gate with the floating diffusion.

First claim

What is claimed is:

1. An image sensor comprising a plurality of pixels, each pixel comprising:
a transfer gate formed on a first surface of a semiconductor substrate;
a floating diffusion region formed in the semiconductor substrate;
a pinned photodiode having a charge accumulation/storage region disposed substantially beneath the transfer gate and a pinning region disposed laterally to the charge accumulation/storage region and spaced away from the first surface, wherein an edge of the transfer gate is disposed adjacent to and spaced away from the floating diffusion region by an intervening semiconductor region configured to provide a potential barrier to charge flow from beneath the transfer gate to the floating diffusion, and
wherein the transfer gate is operable to selectively transfer charge from the charge accumulation/storage region to the floating diffusion region by pumping charge from the buried charge accumulation/storage region underlying the transfer gate, over the potential barrier that is between the transfer gate and the floating diffusion region, and to the floating diffusion region.

2. The image sensor according to claim 1 , wherein a first semiconductor region is disposed beneath the transfer gate and overlies the charge accumulation storage region, and a second semiconductor region is disposed beneath the transfer gate and overlies the first semiconductor region and is laterally adjacent to the intervening semiconductor region, and wherein the first semiconductor region is configured to provide a potential barrier that prevents charge from flowing back toward the charge accumulation/storage region during charge transfer from the second semiconductor region to the floating diffusion via the intervening semiconductor region.

3. The image sensor according to claim 2 , wherein the first and second semiconductor regions, and the intervening semiconductor region all have the same doping type, with the first semiconductor region having a higher dopant concentration than the second semiconductor region, and the second semiconductor region having a higher dopant concentration than the intervening semiconductor region.

4. The image sensor according to claim 1 , wherein the transfer gate is operable to selectively transfer at least a portion of charge accumulated in the charge accumulation/storage region to the floating diffusion region in response to an individual pulse being applied to the transfer gate, by pumping charge (i) from the charge accumulation/storage region to a first potential well in response to the individual pulse pulsing the transfer gate from an OFF state to a given ON state, and (ii) to the floating diffusion from the first potential well over the potential barrier that is between the transfer gate and the floating diffusion region in response to the individual pulse pulsing the transfer gate from said given ON state to an OFF state.

5. An image sensor pixel architecture, comprising:
a floating diffusion formed in a first surface of a semiconductor substrate;
a pinned photodiode comprising a pinning region of a first conductivity type and a photocharge accumulation/storage region of a second conductivity type opposite to the first conductivity type, wherein the pinning region (i) extends along a vertical direction substantially perpendicular to the first surface, and (ii) in a region of the semiconductor substrate spaced away from the first surface, is disposed laterally to the charge accumulation/storage region, and (iii) is configured to form a pinned photodiode with the charge accumulation/storage region such that the photocharge accumulation/storage region is fully depleted when empty of photocharge; and
a transfer gate that is configured to control charge transfer from the photocharge accumulation/storage region of the pinned photodiode to the floating diffusion; and
wherein the floating diffusion is separated from an adjacent edge of a gate dielectric of the transfer gate such that the floating diffusion is not overlapped by the adjacent edge of the gate dielectric of the transfer gate.

6. The image sensor pixel architecture according to claim 5 , wherein the pinning region is configured to sandwich the photocharge accumulation/storage region along at least one lateral direction, wherein p-n junction interfaces formed between the photocharge accumulation/storage region and the pinning region extend along the vertical direction.

7. The image sensor pixel architecture according to claim 6 , wherein the pinning region laterally surrounds the photocharge accumulation/storage region.

8. The image sensor according to claim 5 , wherein the transfer gate is operable to selectively transfer at least a portion of charge accumulated in the charge accumulation/storage region to the floating diffusion region in response to an individual pulse being applied to the transfer gate, by pumping charge (i) from the charge accumulation/storage region to a first potential well in response to the individual pulse pulsing the transfer gate from an OFF state to a given ON state, and (ii) to the floating diffusion from the first potential well over a potential barrier that is between the transfer gate and the floating diffusion region in response to the individual pulse pulsing the transfer gate from said given ON state to an OFF state.

9. A CMOS active pixel image sensor comprising an array of pixels, each pixel configured for selective intra-pixel charge transfer from a respective storage node that is primarily located under a transfer gate of the pixel, wherein the transfer gate is operable to transfer charge from the storage node to a floating diffusion according to a pump gate architecture that is configured to selectively transfer at least a portion of charge accumulated in the storage node to the floating diffusion in response to an individual pulse being applied to the transfer gate, by pumping charge (i) from the storage node to a first potential well in response to the individual pulse pulsing the transfer gate from an OFF state to a given ON state, and (ii) to the floating diffusion from the first potential well over a first potential barrier that is between the transfer gate and the floating diffusion in response to the individual pulse pulsing the transfer gate from said given ON state to an OFF state.

10. The CMOS active pixel image sensor according to claim 9 , wherein the floating gate and the transfer gate do not overlap such that overlap capacitance therebetween is negligible relative to the capacitance of the floating gate.

11. The image sensor pixel architecture according to claim 9 , wherein the pump gate architecture includes a second potential barrier disposed between the storage node and the first potential well, and configured to prevent charge from flowing back toward the storage node during charge transfer from the first potential well to the floating diffusion in response to the transfer gate being pulsed from said given ON state to the OFF state.

12. The image sensor pixel architecture according to claim 11 , wherein said first potential barrier, said second potential barrier, and said first potential well comprise respective semiconductor regions doped at respective concentrations of a first conductivity type, and wherein said floating diffusion and said storage node comprise respective semiconductor regions doped at respective concentrations of a conductivity type opposite to said first conductivity type.

13. The image sensor pixel architecture according to claim 9 , wherein the storage node comprises a doped semiconductor region that forms a p-n junction with a pinning layer of a pinned photodiode.

14. The ima

Assignees

• Dartmouth College

Inventors

• Ma Jiaju
• Fossum Eric R

Classifications

• H10F39/80377

  characterised by the channel of the transistor, e.g. channel having a doping gradient · CPC title

• H10F39/80373

  characterised by the gate of the transistor · CPC title

• H10F39/8063

  Microlenses · CPC title

• H10F39/8053

  Colour filters · CPC title

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title