Techniques for configuring a processor to function as multiple, separate processors

Patent metadata

Field	Value
Publication number	US-11249905-B2
Application number	US-201916562361-A
Country	US
Kind code	B2
Filing date	Sep 5, 2019
Priority date	Sep 5, 2019
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
partitioning a first portion of a set of memory resources included in a processor to generate a plurality of logical memory partitions, wherein each logical memory partition is associated with at least one engine included in a plurality of engines and corresponds to a different address range within a first set of memory addresses, and wherein each address range is for accessing a different subset of cache slices included in a plurality of cache slices;
partitioning a second portion of the set of memory resources to generate a memory section that includes a portion of each cache slice in the plurality of cache slices, wherein the second portion is accessed via a second set of memory addresses for accessing any of the plurality of cache slices, and wherein the second portion is inaccessible via the first set of memory addresses;
receiving a plurality of memory access requests from the plurality of engines; and
transmitting each memory access request included in the plurality of memory access requests to the memory section or to one of the logical memory partitions, wherein each memory access request is serviced by the memory section or the respective logical memory partition.

2. The computer-implemented method of claim 1 , wherein partitioning the first portion of the set of memory resources comprises activating a set of logical boundaries associated with the set of memory resources based on a set of bits, wherein each bit included in the set of bits corresponds to a different logical boundary included in the set of logical boundaries.

3. The computer-implemented method of claim 1 , wherein a first memory access request included in the plurality of memory access requests is transmitted to first logical memory partition included in the plurality of logical memory partitions based on a set of bits, wherein the first portion of the set of memory resources is partitioned based, at least in part, on the set of bits.

4. The computer-implemented method of claim 1 , further comprising translating a first address associated with a first memory access request included in the plurality of memory access requests based on a set of bits to generate a second address, wherein the second address is associated with a memory location residing within a first logical memory partition included in the plurality of logical memory partitions, and the set of memory resources is partitioned based, at least in part, on the set of bits.

5. The computer-implemented method of claim 1 , further comprising designating the second portion of the set of memory resources for access by an authorized entity, wherein the second portion of the set of memory resources is not included in the plurality of logical memory partitions, and the authorized entity partitions the first portion of the set of memory resources to generate the plurality of logical memory partitions.

6. The computer-implemented method of claim 1 , further comprising:
determining a first fault associated with a first memory access request that is associated with a memory location residing within a first logical memory partition included in the plurality of logical memory partitions;
translating a virtual fault identifier corresponding to the first fault to a global fault identifier corresponding to the first fault; and
resetting a first engine based on the global fault identifier, wherein the first engine is included in the plurality of engines and is configured to access the first logical memory partition.

7. The computer-implemented method of claim 1 , further comprising translating a virtual fault identifier included in a local address space associated with a first logical memory partition included in the plurality of logical memory partitions to generate a global fault identifier included in a global address space associated with the set of memory resources, wherein the virtual fault identifier is generated by the first logical memory partition when servicing a first memory access request included in the plurality of memory access requests.

8. The computer-implemented method of claim 1 , further comprising:
configuring a first logical memory partition included in the plurality of logical memory partitions to include a first region of memory that stores data associated with a first engine included in the plurality of engines; and
configuring the first logical memory partition to include a second region of memory that stores data associated with a second engine included in the plurality of engines.

9. The computer-implemented method of claim 8 , wherein the first engine executes a first set of processing tasks associated with a first processing context using the first region of memory, and the second engine executes a second set of processing tasks associated with a second processing context using the second region of memory.

10. The computer-implemented method of claim 1 , further comprising:
configuring a first logical memory partition included in the plurality of logical memory partitions to include a first region of memory that stores data associated with a first processing subcontext that is derived from a first processing context; and
configuring the first logical memory partition to include a second region of memory that stores data associated with a second processing subcontext that also is derived from the first processing context.

11. A non-transitory computer-readable medium storing program instructions that, when executed by a processor, cause the processor to perform steps of:
partitioning a first portion of a set of memory resources included in a processor to generate a plurality of logical memory partitions, wherein each logical memory partition is associated with at least one engine included in a plurality of engines and corresponds to a different address range within a first set of memory addresses, and wherein each address range is for accessing a different subset of cache slices included in a plurality of cache slices;
partitioning a second portion of the set of memory resources to generate a memory section that includes a portion of each cache slice in the plurality of cache slices, wherein the second portion is accessed via a second set of memory addresses for accessing any of the plurality of cache slices, and wherein the second portion is inaccessible via the first set of memory addresses; and
transmitting each memory access request included in a plurality of memory access requests received from the plurality of engines to the memory section or to one of the logical memory partitions, wherein each memory access request is serviced by the memory section or the respective logical memory partition.

12. The non-transitory computer-readable medium of claim 11 , wherein the step of partitioning the first set of the set of memory resources comprises activating a set of logical boundaries associated with the set of memory resources based on a set of bits, wherein each bit included in the set of bits corresponds to a different logical boundary included in the set of logical boundaries.

13. The non-transitory computer-readable medium of claim 11 , wherein a first memory access request included in the plurality of memory access requests is transmitted to a first logical memory partition included in the plurality of logical memory partitions based on a set of bits, wherein the first set of the set of memory resources is partitioned based, at least in part, on the set of bits.

14. The non-transitory computer-readable medium of claim 11 , further comprising the step of designating the second portion of the set of memory resources for a

Assignees

• Nvidia Corp

Inventors

• Duluk Jr Jerome F
• Palmer Gregory Scott
• Evans Jonathon Stuart Ramsey
• Singh Shailendra
• Duncan Samuel H
• Gandhi Wishwesh Anil
• Shah Lacky V
• Rock Eric
• Su Feiqi
• Deming James Leroy
• Menezes Alan
• Vaidya Pranav
• Joginipally Praveen
• Purcell Timothy John
• Mandal Manas

Classifications

• G06F2212/1041

  Resource optimization · CPC title

• G06F2209/5017

  Task decomposition · CPC title

• G06F9/5077 Primary

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F12/0646 Primary

  Configuration or reconfiguration · CPC title

• G06F9/5027 Primary

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title