Accelerator interconnect assignments for virtual environments

Patent metadata

Field	Value
Publication number	US-11249779-B2
Application number	US-201715853670-A
Country	US
Kind code	B2
Filing date	Dec 22, 2017
Priority date	Sep 1, 2017
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

A computer system may comprise a multi-chip package (MCP), which includes multi-core processor circuitry and hardware accelerator circuitry. The multi-core processor circuitry may comprise a plurality of processing cores, and the hardware accelerator circuitry may be coupled with the multi-core processor circuitry via one or more coherent interconnects and one or more non-coherent interconnects. A coherency domain of the MCP may be extended to encompass the hardware accelerator circuitry, or portions thereof An interconnect selection module may select an individual coherent interconnect or an individual non-coherent interconnect based on application requirements of an application to be executed and a workload characteristic policy. Other embodiments are described and/or claimed.

First claim

The invention claimed is:

1. A multi-chip package (MCP) to be employed in a computer system, the MCP comprising:
multi-core processor circuitry comprising a plurality of processing cores, wherein one or more processing cores of the plurality of processing cores are to implement virtual machines (VMs); and
hardware accelerator circuitry coupled with the multi-core processor circuitry via one or more coherent interconnects (IXs) and one or more non-coherent IXs, wherein individual coherent IXs of the one or more coherent IXs and individual non-coherent IXs of the one or more non-coherent IXs are bound to individual VMs based on workload characteristics of application functions of an application to be executed in the individual VMs, and the individual coherent IXs include one or more IX technologies that maintain cache coherence and the individual non-coherent IXs include one or more IX technologies that do not maintain cache coherence.

2. The MCP of claim 1 , wherein the computer system comprises:
system memory circuitry coupled with the multi-core processor circuitry; and
a coherency domain, wherein the coherency domain comprises the system memory, last level cache (LLC) circuitry of the multi-core processor circuitry, the one or more coherent IXs, and cache circuitry of the hardware accelerator circuitry.

3. The MCP of claim 1 , wherein the individual VMs comprise a set of virtual input/output (vIO) ports, wherein each vIO port of the set of vIO ports is bound to a coherent IX of the one or more coherent IXs or a non-coherent IX of the one or more non-coherent IXs according to a workload characteristic policy (WCP), wherein the WCP is to define a set of workload criteria for individual application functions of the application.

4. The MCP of claim 3 , wherein the hardware accelerator circuitry comprises:
device interface unit (DIU) circuitry; and
accelerated function unit (AFU) circuitry coupled with the DIU circuitry via programmable core cache interface (CCI-P) circuitry, wherein the AFU circuitry comprises one or more memory cells to be loaded with an accelerator image of a plurality of accelerator images.

5. The MCP of claim 4 , wherein the CCI-P circuitry is to abstract the one or more coherent IXs and the one or more non-coherent IXs into individual virtual channels (VCs), wherein the individual VCs are to communicatively couple the individual application functions to individual accelerator functions of a plurality of accelerator functions.

6. The MCP of claim 5 , wherein an individual processing core of the plurality of processing cores is to implement an IX selection module to:
select the individual coherent IXs and the individual non-coherent IXs to be bound to corresponding ones of the individual VMs, wherein, to select the individual coherent IXs or the individual non-coherent IXs, the IX selection module is to:
assign individual coherent IXs and the individual non-coherent IXs to corresponding ones of the individual VCs based on current workload characteristics and the WCP.

7. The MCP of claim 6 , wherein, to select an individual coherent IX or an individual non-coherent IX, the IX selection module is to:
select, as an initial IX before execution of an application function of the application, one of the individual coherent IX or the individual non-coherent IX based on an anticipated workload of the application function, wherein the anticipated workload is based on application requirements; and
select another IX of the one or more coherent IXs or the one or more non-coherent IXs when current workload characteristics of the application function exceed a threshold defined by the application requirements.

8. The MCP of claim 4 , wherein the DIU circuitry is to:
implement interface protocols for the one or more coherent IXs and the one or more non-coherent IXs; and
exchange information between an operator platform and the AFU circuitry, wherein the information comprises security information, error monitoring information, performance monitoring information, power and thermal management information, and AFU configuration information.

9. The MCP of claim 4 , wherein the DIU circuitry comprises:
DIU cache;
one or more non-coherent cache controllers corresponding to the one or more non-coherent IXs;
one or more coherent cache controllers corresponding to the one or more coherent IXs, and wherein the one or more coherent cache controllers are to issue read and write requests to a coherent system memory of the computer system and perform bus snooping operations on the DIU cache.

10. The MCP of claim 1 , wherein:
the one or more coherent IXs are Intel® Ultra Path Interface (UPI) IXs, Intel® Accelerator Link (IAL) IXs, or Common Application Programming Interface (CAPI) IXs;
the one or more non-coherent IXs are peripheral component interconnect express (PCIe) IXs; and
the hardware accelerator circuitry is a field programmable gate array (FPGA).

11. A computer system, comprising:
one or more network interface controllers (NICs);
system memory circuitry; and
one or more multi-chip packages (MCPs) communicatively coupled to one another and communicatively coupled with the system memory circuitry, wherein at least one MCP of the one or more MCPs is communicatively coupled with the one or more NICs, and wherein each MCP of the one or more MCPs comprises:
multi-core processor circuitry comprising a plurality of processing cores,

wherein one or more processing cores of the plurality of processing cores are to implement individual virtual machines (VMs);
hardware accelerator circuitry coupled with the multi-core processor circuitry via one or more coherent interconnects (IXs) and one or more non-coherent IXs, wherein the one or more coherent IXs include at least one IX technology that maintain cache coherence and the one or more non-coherent IXs include at least one IX technology that do not maintain cache coherence; and
a coherency domain, wherein the coherency domain comprises the system memory, last level cache (LLC) circuitry of the multi-core processor circuitry, the one or more coherent IXs, and cache circuitry of the hardware accelerator circuitry, and
wherein individual coherent IXs of the one or more coherent IXs and individual non-coherent IXs of the one or more non-coherent IXs are bound to individual VMs based on workload characteristics of application functions of an application to be executed in the individual VMs.

12. The computer system of claim 11 , wherein the individual VMs comprise a set of virtual input/output (vIO) ports, wherein each vIO port of the set of vIO ports is bound to a coherent IX of the one or more coherent IXs or a non-coherent IX of the one or more non-coherent IXs according to a workload characteristic policy (WCP), wherein the WCP is to define a set of workload criteria for individual application functions of the application.

13. The computer system of claim 12 , wherein the hardware accelerator circuitry comprises:
device interface unit (DIU) circuitry; and
accelerated function unit (AFU) circuitry coupled with the DIU circuitry via programmable core cache interface (CCI-P) circuitry, wherein the AFU circuitry comprises one or more memory cells to be loaded with an accelerator image of a plurality of accelerator images.

14. The computer system of claim 13 , wherein an individual processing core of the plurality of processing cores is to implement an IX selection module to:
select individual coherent IXs and individual non-coherent IXs to be bound to corresponding ones of the individual VMs.

15. The computer system of claim 14 , wherein the CCI-P circ

Assignees

• Intel Corp

Inventors

• Palermo Stephen
• Rogers Gerald
• Chien Shih-Wei
• Venkatesan Namakkal

Classifications

• G06F9/505 Primary

  considering the load · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F9/50

  Allocation of resources, e.g. of the central processing unit [CPU] · CPC title