Memory device resilient to cyber-attacks and malfunction

Patent metadata

Field	Value
Publication number	US-11249689-B2
Application number	US-202017066599-A
Country	US
Kind code	B2
Filing date	Oct 9, 2020
Priority date	Jan 22, 2020
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.

First claim

What is claimed is:

1. A non-volatile memory (NVM) integrated circuit device comprising:
an NVM array of memory cells, the NVM array partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack; and
a processing device coupled to the NVM array, the processing device to:
enable a host microcontroller to execute in place the first firmware stack based on a first set of logical addresses that is mapped to the first physical region;
track accesses to the first set of logical addresses;
detect a certain number of the accesses or a certain type of the accesses; and
in response to detecting one of the certain number of the accesses or the certain type of the accesses, initiate a recovery operation to remap the first set of logical addresses to the second physical region.

2. The NVM integrated circuit device of claim 1 , wherein the second firmware stack is executed in place to resolve an unexpected event detected during the execution of the first firmware stack.

3. The NVM integrated circuit device of claim 1 wherein, after the recovery operation is complete, the processing device is further to remap the first set of logical addresses back to the first physical region in order to enable the host microcontroller to execute a reset of the first firmware stack stored therein.

4. The NVM integrated circuit device of claim 1 wherein, after the first set of logical addresses is remapped to the second physical region, the second firmware stack is locked to prevent writing thereto.

5. The NVM integrated circuit device of claim 1 , wherein the processing device is further to:
detect the certain number of the accesses based on a counter coupled to the processing device; and
reset the counter only in response to a cryptographically authenticated request received from a remote authority server.

6. The NVM integrated circuit device of claim 1 , wherein the NVM integrated circuit device is a system-on-chip (SoC) device.

7. The NVM integrated circuit device of claim 1 , wherein the NVM array further comprises a third physical region to store a third firmware stack that is write protected from the host microcontroller.

8. The NVM integrated circuit device of claim 7 , wherein prior to the recovery operation, the processing device is further to perform one or more of:
perform a hash-based validation of the second firmware stack against the third firmware stack; and
replace the second firmware stack with the third firmware stack.

9. The NVM integrated circuit device of claim 1 , wherein the processing device is to initiate the recovery operation in response to detection of one of an unapproved access by the host microcontroller or a malfunction of the NVM integrated circuit device.

10. The NVM integrated circuit device of claim 9 , wherein the detection is based on execution reports generated by using one or more of:
the certain number of accesses that are tracked against a range of logical addresses, of the first set of logical addresses, identified as being of interest; and
a self-consistency model based on comparison of boot or non-boot runtime behavior and abnormal runtime behavior.

11. A method of operating a non-volatile memory (NVM) integrated circuit device, the method comprising:
executing in place, by a host microcontroller, a first firmware stack stored within a first physical region of an NVM array of memory cells, wherein a first set of logical addresses is mapped to the first physical region; and
executing recovery logic, wherein executing the recovery logic comprises:
tracking accesses to the first set of logical addresses by the host microcontroller;
detecting a certain number of the accesses or a certain type of the accesses; and
in response to detecting one of the certain number of the accesses or the certain type of the accesses, initiating a recovery operation that comprises remapping the first set of logical addresses to a second physical region of the NVM array, wherein the second physical region stores a second firmware stack.

12. The method of claim 11 , wherein a third physical region of the NVM array stores a third firmware stack that is not accessible by the host microcontroller, and wherein the method further comprises:
detecting that the host microcontroller is denying the NVM integrated circuit device a networked connection to a remote authority sever; and
prior to initiating the recovery operation, replacing the second firmware stack with the third firmware stack from the third physical region.

13. The method of claim 11 , wherein a third physical region of the NVM array stores a third firmware stack that is not accessible by the host microcontroller, and wherein the method further comprises, prior to initiating the recovery operation, performing a hash-based validation of the second firmware stack against the third firmware stack.

14. The method of claim 11 , further comprising securing, using cryptographic operations, read requests and write requests directed to the first set of logical addresses.

15. The method of claim 11 , wherein detecting the certain type of the accesses comprises determining the amount of data read out of the NVM array since boot up.

16. The method of claim 11 , wherein executing the recovery logic is performed by executing an embedded code stored within one of a read only memory (ROM) or the NVM array.

17. The method of claim 11 , further comprising executing in place the second firmware stack by the host microcontroller.

18. The method of claim 17 , further comprising:
receiving a reset of the first firmware stack from a remote authority server, as part of the recovery operation; and
remapping the first set of logical addresses back to the first physical region in order to enable to host microcontroller to execute the reset of the first firmware stack stored therein.

19. The method of claim 11 , wherein executing the recovery logic comprises initiating the recovery operation in response to detecting one of an unapproved access by the host microcontroller or a malfunction of the NVM integrated circuit device.

20. The method of claim 19 , wherein detecting one of the unapproved access by the host microcontroller or the malfunction of the NVM integrated circuit device comprises one or more of:
tracking the certain number of the accesses against a range of logical addresses, of the first set of logical addresses, identified as being of interest; and
executing a self-consistency model based on comparison of boot or non-boot runtime behavior and abnormal runtime behavior.

Assignees

• Cypress Semiconductor Corp

Inventors

• Ostrikov Sergey
• Rosner Stephan
• Avanindra Avi
• Van Antwerpen Hans

Classifications

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• H04L9/3236

  using cryptographic hash functions · CPC title

• G06F12/10

  Address translation · CPC title

• G06F3/062

  Securing storage systems · CPC title

• G06F2212/7202

  Allocation control and policies · CPC title