Serial memory device single-bit or plurality-bit serial I/O mode selection

Patent metadata

Field	Value
Publication number	US-11249678-B2
Application number	US-201916523429-A
Country	US
Kind code	B2
Filing date	Jul 26, 2019
Priority date	Jul 26, 2019
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

Methods and apparatuses for memory device mode selection in a serial memory device are presented. Memory device configuration information may be retrieved in response to a memory device initialization condition, and a configuration register bit mask that is included in the memory device configuration information may then be written to a configuration register of the memory device. A write command that may also be included in the memory device configuration information may be used to write the configuration bit mask to the configuration register. The serial memory device may be a serial flash memory. The configuration register bit mask may include an I/O mode bit setting that indicates enabling the memory to operate in a quad-bit I/O mode or other multi-bit serial I/O mode instead of a single-bit serial I/O mode.

First claim

What is claimed is:

1. A method, comprising:
retrieving, by a processor system, memory device configuration information in response to a memory device initialization condition, the memory device configuration information including input/output (I/O) mode information and a write command;
writing, by the processor system, to a configuration register of a serial memory device using the write command, based on the I/O mode information, to indicate enablement of a plural-bit I/O mode, wherein the memory device configuration information further includes a wait time, and;
determining, after writing the configuration register bit mask to a configuration register and elapse of the wait time, whether an I/O mode bit of the configuration register is set to indicate enablement of the plural-bit I/O mode.

2. The method of claim 1 , wherein:
the memory device initialization condition comprises a boot-up of an apparatus incorporating the memory device and the processor system; and
retrieving the memory device configuration information comprises reading the memory device configuration information from a boot sector of the memory device.

3. The method of claim 2 , wherein reading the memory device configuration information from the boot sector of the memory device comprises reading using a memory single-bit I/O mode.

4. The method of claim 1 , wherein retrieving the memory device configuration information comprises:
obtaining, by the processor system, the memory device configuration information from a remote data storage source via a data communication network;
storing, by the processor system, the memory device configuration information in a boot sector of the memory device; and
reading, by the processor system, the memory device configuration information from the boot sector of the memory device in response to the memory device initialization condition.

5. The method of claim 4 , wherein reading the memory device configuration information from the boot sector of the memory device comprises reading using a single-bit I/O mode.

6. The method of claim 4 , wherein storing the memory device configuration information in the boot sector of the memory device comprises writing using a single-bit I/O mode.

7. A method, comprising:
retrieving, by a processor system, memory device configuration information in response to a memory device initialization condition, the memory device configuration information including input/output (I/O) mode information and a write command;
writing, by the processor system, to a configuration register of a serial memory device using the write command, based on the I/O mode information, to indicate enablement of a plural-bit I/O mode;
reading device identification information from the memory device;
determining whether the device identification information matches an identification portion of the memory device configuration information; and
wherein writing the configuration register bit mask to the configuration register comprises writing the configuration register bit mask to the configuration register in response to determining the identification information matches the identification portion of the memory device configuration information.

8. An apparatus, comprising:
a host coupled to a serial memory device via a link, wherein the host comprises a processor system configured to
retrieve memory device configuration information in response to a memory device initialization condition, the memory device configuration information including input/output (I/O) mode information and a write command;
write to a configuration register of the memory device using the write command, based on the I/O mode information, to indicate enablement of a plural-bit I/O mode;
read device identification information from the memory device;
determine whether the device identification information matches an identification portion of the memory device configuration information; and
write the configuration register bit mask to the configuration register in response to determining the identification information matches the identification portion of the memory device configuration information.

9. The apparatus of claim 8 , further comprising one of a computing system, a mobile computing system, an Internet of Things (IoT) device, a virtual reality system, or an augmented reality system incorporating the host, the memory, and the link, wherein the processor system is configured to perform a computing function of the one of the computing system, the mobile computing system, the Internet of Things device, the virtual reality system, or the augmented reality system.

10. The apparatus of claim 8 , wherein:
the memory device initialization condition comprises a boot-up of an apparatus incorporating the memory device and the processor system; and
retrieving the memory device configuration information comprises reading the memory device configuration information from a boot sector of the memory device.

11. The apparatus of claim 10 , wherein reading the memory device configuration information from the boot sector of the memory device comprises reading using a memory single-bit I/O mode.

12. The apparatus of claim 8 , wherein the processor system is configured to retrieve the memory device configuration information by being configured to:
obtain the memory device configuration information from a remote data storage source via a data communication network;
store the memory device configuration information in a boot sector of the memory device; and
read the memory device configuration information from the boot sector of the memory device in response to the memory device initialization condition.

13. The apparatus of claim 12 , wherein the processor system is configured to read the memory device configuration information from the boot sector of the memory device using a single-bit I/O mode.

14. The apparatus of claim 12 , wherein the processor system is configured to store the memory device configuration information in the boot sector of the memory device using a single-bit I/O mode.

15. An apparatus, comprising:
a host coupled to a serial memory device via a link, wherein the host comprises a processor system configured to
retrieve memory device configuration information in response to a memory device initialization condition, the memory device configuration information including input/output (I/O) mode information and a write command;
write to a configuration register of the memory device using the write command, based on the I/O mode information, to indicate enablement of a plural-bit I/O mode, wherein the memory device configuration information further includes a wait time, and the method further includes determining, after writing the configuration register bit mask to a configuration register and elapse of the wait time, whether an I/O mode bit of the configuration register is set to indicate enablement of the plural-bit I/O mode.

16. An apparatus, comprising:
a serial memory device; and
a processor system configured to retrieve memory device configuration information in response to a memory device initialization condition, the memory device configuration information including input/output (I/O) mode information and a write command, the processor system further configured to write to a configuration register of the memory device using the write command, based on the I/O mode information, to indicate enablement of a plural-bit I/O mode;
wherein the memory device configuration information further includes a wait time, and the processor system is further configured to determine, after writing the c

Assignees

• Qualcomm Inc

Inventors

• Pillai Sunil
• Kumar Tarun
• Karmakar Gopal

Classifications

• G11C16/32

  Timing circuits · CPC title

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C5/066 Primary

  Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals · CPC title