Localized functionalization of nanotextured surfaces

US11247896B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11247896-B2
Application numberUS-201916526964-A
CountryUS
Kind codeB2
Filing dateJul 30, 2019
Priority dateJul 31, 2018
Publication dateFeb 15, 2022
Grant dateFeb 15, 2022

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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A material with a nanotexture comprising structures extending from a substrate. The structures are modified by coating the nanotexture with a protective coating and partially removing the coating, exposing a portion of the structure for functionalization.

First claim

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We claim: 1. A method for functionalizing a nanotextured material comprising: forming a nanotextured material having a plurality of structures extending in a first dimension and each of the plurality of structures having a distal portion; applying a resist coating on the nanotextured material, the resist coating leaving an uncoated distal portion of the plurality of structures corresponding to at least some of the distal portions of the plurality of structures; modifying the uncoated distal portions with a first functional group; and removing the resist coating. 2. The method of claim 1 , wherein applying the resist coating comprises applying the resist coating comprises spin coating the nanotextured material. 3. The method of claim 2 , wherein the resist coating fills space between each of the plurality of structures. 4. The method of claim 2 , wherein the exposed distal portions are functionalized with the first function group and remaining portions of the plurality of structures are not functionalized with the first functional group. 5. The method of claim 1 , wherein applying the resist coating further comprises removing a portion of the resist coating to expose the exposed distal portions. 6. The method of claim 1 , further comprising: prior to applying the resist coating, the nanotextured material is washed with tolulene; and modifying the exposed distal portions comprises silanization, wherein the silanization comprises application of a silane solution having 0.001% to 1% v/v silane in a toluene solvent. 7. The method of claim 1 , further comprising positioning a polymeric network on the nanostructures. 8. The method of claim 1 , wherein a mask is applied to the exposed distal portions forming masked distal portions and further comprising application of a second etching after removal of the resist coating, the second etching removing proximate portions of the nanostructures that are not the masked distal portions. 9. A method for functionalizing a nanotextured material comprising: forming a nanotextured material having a plurality of structures extending in a first dimension and each of the plurality of structures having a distal portion; forming a resist coating on the nanotextured material by applying the resist coating to the nanotextured material and removing a portion of the resist coating, exposing distal portions; modifying the exposed distal portions by silanization; and removing the resist coating. 10. The method of claim 9 , wherein the exposed distal portions are functionalized with the first function group and remaining portions of the plurality of structures are not functionalized with the first functional group. 11. The method of claim 9 , wherein the plurality of structures are heterogeneous. 12. The method of claim 9 , wherein the silanization comprises application of a silane solution having 0.001% to 1% v/v silane in a first organic solvent. 13. The method of claim 12 , wherein, prior to applying the resist coating, the nanotextured material is washed with the first organic solvent, the first organic solvent comprising toluene. 14. The method of claim 13 , wherein the silane is a chlorosilane. 15. A method for functionalizing a nanotextured material comprising: forming a nanotextured material having a plurality of structures extending in a first dimension and each of the plurality of structures having a distal portion; applying a resist coating on the nanotextured material, wherein at least some of the distal portions of the plurality of structures are exposed beyond the resist coating; modifying the exposed distal portions with a first functional group; removing the resist coating; and applying a mask to the exposed distal portions forming masked distal portions and further comprising application of a second etching after removal of the resist coating, the second etching removing proximate portions of the nanostructures that are not the masked distal portions. 16. The method of claim 15 , wherein the resist coating fills space between each of the plurality of structures. 17. The method of claim 15 , modifying the exposed distal portions comprises silanization. 18. The method of claim 17 , wherein the silanization comprises application of a silane solution having 0.001% to 1% v/v silane in a first organic solvent. 19. The method of claim 15 , wherein the exposed distal portions are functionalized with the first function group and remaining portions of the plurality of structures are not functionalized with the first functional. 20. The method of claim 15 , wherein, prior to applying the resist coating, the nanotextured material is washed with the first organic solvent, the first organic solvent comprising toluene.

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What does patent US11247896B2 cover?
A material with a nanotexture comprising structures extending from a substrate. The structures are modified by coating the nanotexture with a protective coating and partially removing the coating, exposing a portion of the structure for functionalization.
Who is the assignee on this patent?
Uchicago Argonne Llc
What technology area does this patent fall under?
Primary CPC classification B81C1/00111. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Feb 15 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).