Process for managing the start-up of a phase-locked loop, and corresponding integrated circuit

Patent metadata

Field	Value
Publication number	US-11245405-B2
Application number	US-202117352849-A
Country	US
Kind code	B2
Filing date	Jun 21, 2021
Priority date	Jun 24, 2020
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation.

First claim

The invention claimed is:

1. A process for managing operation of a startup phase for a phase-locked loop (PLL) circuit, said PLL circuit including a phase comparator and a voltage-controlled oscillator, comprising:
supplying control pulses by the phase comparator, wherein during each of the control pulses an output signal frequency of the voltage-controlled oscillator increases, wherein said increase comprises applying a pre-charge current at an oscillator input;
determining at least one time variation of said output signal frequency; and
adjusting at least one intensity of the pre-charge current depending on said determined at least one time variation so as to cause said determined at least one time variation to approach a reference time variation.

2. The process according to claim 1 , wherein adjusting comprises:
decreasing said at least one intensity if the determined at least one time variation is greater than the reference time variation; and
increasing said at least one intensity if the determined at least one time variation is less than the reference time variation.

3. The process according to claim 1 , further comprising:
supplying a reference clock signal to the phase comparator of the PLL circuit; and
supplying a feedback signal to the phase comparator of the PLL circuit, said feedback signal derived from a first counter forming a first divider of an output signal of the voltage-controlled oscillator;
wherein determining the at least one time variation comprises:
determining at least two current counting values provided by the first counter respectively upon the occurrence, during a control pulse, of at least two edges belonging to at least two different periods of the reference clock signal; and
determining said at least one time variation from said at least two current counting values.

4. The process according to claim 3 , wherein adjusting comprises:
decreasing said at least one intensity if the determined at least one time variation is greater than the reference time variation; and
increasing said at least one intensity if the determined at least one time variation is less than the reference time variation.

5. The process according to claim 1 , further comprising:
supplying a reference clock signal to the phase comparator of the PLL circuit;
wherein determining said at least one time variation comprises:
after supplying a first control pulse, performing a first count of a first number of output signal pulses of the voltage-controlled oscillator between two edges belonging to two successive periods of the reference clock signal;
wherein any increase in the output signal frequency is inhibited during said performing the first count;
then, after removing the inhibition and after supplying a subsequent second control pulse, performing a second count of a second number of output signal pulses of the voltage-controlled oscillator between two edges belonging to two successive periods of the reference clock signal;
wherein any increase in the output signal frequency is inhibited during said performing the second count; and
determining said at least one time variation from the first number and the second number.

6. The process according to claim 5 , wherein adjusting comprises:
decreasing said at least one intensity if the determined at least one time variation is greater than the reference time variation; and
increasing said at least one intensity if the determined at least one time variation is less than the reference time variation.

7. The process according to claim 1 , further comprising:
supplying a reference clock signal having a duty cycle of 50% to the phase comparator of the PLL circuit;
resetting, during said start-up phase, a first counter at each first-type edge of the reference clock signal, wherein said first counter forms a first divider of an output signal of the voltage-controlled oscillator;
supplying a control pulse by the phase comparator at each second-type edge of the reference signal, said phase comparator receiving the reference signal and a feedback signal derived from the first divider; and
wherein determining said at least one time variation comprises:
determining at least two current counting values provided by the first counter respectively upon the occurrence of at least two control pulses; and
determination said at least one time variation from said at least two current counting values.

8. The process according to claim 7 , wherein adjusting comprises:
decreasing said at least one intensity if the determined at least one time variation is greater than the reference time variation; and
increasing said at least one intensity if the determined at least one time variation is less than the reference time variation.

9. The process according to claim 1 , further comprising, during said start-up phase:
supplying a reference clock signal having a duty cycle of 50% to the phase comparator of the PLL circuit;
resetting a first counter at each first-type edge of the reference clock signal, said first counter forming a first divider of an output signal of the voltage-controlled oscillator;
supplying a control pulse at each second-type edge of the reference signal by the phase comparator, said phase comparator receiving the reference signal and a feedback signal derived from the first divider; and
wherein determining said at least one time variation comprises:
after supplying a first control pulse, performing a first count of a first number of output signal pulses of the voltage-controlled oscillator between two edges of the reference clock signal spaced apart by half a period of the reference clock signal;
after supplying a subsequent second control pulse, performing a second count of a second number of output signal pulses of the voltage-controlled oscillator between two of the reference clock signal spaced apart by half a period of the reference clock signal; and
determining said at least one time variation from the first number and the second number.

10. The process according to claim 9 , wherein adjusting comprises:
decreasing said at least one intensity if the determined at least one time variation is greater than the reference time variation; and
increasing said at least one intensity if the determined at least one time variation is less than the reference time variation.

11. The process according to claim 1 , further comprising:
applying the pre-charge current to a resistive capacitive filter connected at the oscillator input, wherein the resistive capacitive filter comprises:
a first branch connected between said oscillator input and ground and including a resistive network connected in series with a first capacitor having a first capacitive value, said resistive network including a first resistor connected between said oscillator input and an intermediate node and having a first resistive value and a second resistor connected between the intermediate node and the first capacitor and having a second resistive value; and
a second branch connected between said oscillator input and ground and including a second capacitor having a second capacitive value;

wherein the first capacitive value is equal to a times the second capacitive value, and the first resistive value is equal to a times the second resistive value, and
wherein said pre-charge current is applied to said intermediate node.

12. The process according to claim 1 , further comprising:
supplying a feedback signal to the phase comparator of the PLL circuit, said feedback signal derived from a first counter forming a first divider of an output signal of the voltage-controlled oscillator; and
wherein said start-up phase en

Assignees

• St Microelectronics Rousset

Inventors

• Gailhard Bruno
• Truphemus Laurent
• Eva Christophe

Classifications

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L7/101 Primary

  using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop (H03L7/113, H03L7/187 take precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/181

  a numerical count result being used for locking the loop, the counter counting during fixed time intervals {(H03L7/1806 takes precedence)} · CPC title