Phase lock loop circuit based signal generation in an optical measurement system

Patent metadata

Field	Value
Publication number	US-11245404-B2
Application number	US-202117202524-A
Country	US
Kind code	B2
Filing date	Mar 16, 2021
Priority date	Mar 20, 2020
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

An exemplary system includes a PLL circuit and a precision timing circuit connected to the PLL circuit. The PLL circuit has a PLL feedback period defined by a reference clock and includes a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase, and a feedback divider configured to be clocked by a single fine phase signal included in the plurality of fine phase signals and have a plurality of feedback divider states during the PLL feedback period. The precision timing circuit is configured to generate a timing pulse and set, based on a first combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the timing pulse within the PLL feedback period.

First claim

What is claimed is:

1. A system comprising:
a phase lock loop (PLL) circuit having a PLL feedback period defined by a reference clock and comprising:
a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase, and
a feedback divider configured to be clocked by a single fine phase signal included in the plurality of fine phase signals and have a plurality of feedback divider states during the PLL feedback period; and

a precision timing circuit connected to the PLL circuit and configured to
generate a timing pulse, and
set, based on a first combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the timing pulse within the PLL feedback period.

2. The system of claim 1 , wherein the precision timing circuit is further configured to:
generate an additional timing pulse, and
set, based on a second combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the additional timing pulse within the PLL feedback period, the second combination being different than the first combination to cause the temporal position of the additional timing pulse to be different than the temporal position of the timing pulse.

3. The system of claim 2 , wherein:
the timing pulse is configured to trigger a start of an output pulse used by a component within the system; and
the additional timing pulse is configured to trigger an end of the output pulse used by the component within the system.

4. The system of claim 1 , wherein the precision timing circuit is configured to provide the timing pulse as an output pulse used by a component within the system.

5. The system of claim 1 , wherein:
the timing pulse is included in a sequence of timing pulses generated by the precision timing circuit and each configured to have a same temporal position within the PLL feedback period; and
the precision timing circuit is further configured to
receive a command to adjust the temporal position within the PLL feedback period,
update, in response to receiving the command, the first combination to include one or more of a different one of the fine phase signals or a different one of the feedback divider states, and
adjust, based on the updated first combination, the temporal position of the timing pulses generated subsequent to the updating.

6. The system of claim 5 , wherein the precision timing circuit is configured to automatically receive the command from another component in the system without input being provided by a user of the system.

7. The system of claim 1 , further comprising:
a photodetector; and
a time-to-digital converter (TDC) configured to measure a time difference between an occurrence of a light pulse and an occurrence of a photodetector output pulse generated by the photodetector and indicating that the photodetector has detected a photon from the light pulse after the light pulse is scattered by a target.

8. The system of claim 7 , further comprising a timestamp generation circuit configured to:
generate, based on a subset of the fine phase signals that define a plurality of fine states for the plurality of fine phase signals, a timestamp signal bus representative of a plurality of timestamp symbols; and
transmit the timestamp signal bus to the TDC.

9. The system of claim 8 , wherein the timestamp generation circuit comprises:
a course counter configured to be clocked by one of the plurality of fine phase signals and receive a load signal generated by the feedback divider, the load signal configured to reset the course counter at a beginning of each PLL feedback period, the course counter configured to output a course count signal comprising a course count up to a maximum value associated with the course counter;
a first register configured to sample the course count signal to generate a course early signal; and
a second register configured to sample the course early signal to generate a course late signal;
wherein the timestamp signal bus comprises the subset of fine phase signals, the course early signal, and the course late signal.

10. The system of claim 8 , wherein the TDC is configured to measure the time difference between the occurrence of the light pulse and the occurrence of the photodetector output pulse by:
receiving the photodetector output pulse; and
recording a particular timestamp symbol included in the plurality of timestamp symbols that temporally corresponds to when the photodetector output pulse is received.

11. The system of claim 10 , further comprising a signal processing circuit configured to decode the particular timestamp symbol recorded by the TDC into a timestamp representative of when the photodetector output pulse is received.

12. The system of claim 8 , wherein:
the photodetector is included in an array of photodetectors;
the TDC is included in an array of TDCs; and
the timestamp generation circuit is further configured to provide the timestamp signal bus to each TDC included in the array of TDCs.

13. The system of claim 7 , wherein the photodetector comprises:
a single photon avalanche diode (SPAD); and
a fast gating circuit configured to arm and disarm the SPAD.

14. The system of claim 13 , wherein the timing pulse or an output pulse having a start time or an end time defined by the temporal position of the timing pulse is configured to be used as a gate pulse configured to trigger the arming and disarming of the SPAD.

15. The system of claim 7 , wherein the timing pulse or an output pulse having a start time or an end time defined by the temporal position of the timing pulse is configured to be used as a calibration pulse for one or more of the TDCs or another component of the system.

16. The system of claim 7 , wherein the timing pulse or an output pulse having a start time or an end time defined by the temporal position of the timing pulse is configured to be used to trigger a light source to output the light pulse.

17. The system of claim 7 , wherein the photodetector is included in a wearable device configured to be worn by a user.

18. The system of claim 17 , wherein the wearable device includes a head-mountable component configured to be worn on a head of the user.

19. The system of claim 1 , wherein:
a total number of fine phase signals included in the plurality of fine phase signals is N;
a total number of feedback divider states is M; and
the setting of the temporal position comprises selecting, based on the first combination, one of N times M possible temporal positions within the PLL feedback period.

20. The system of claim 19 , wherein N is 16 and M is 20.

21. The system of claim 1 , wherein the feedback divider comprises a linear feedback shift register.

22. The system of claim 1 , wherein the precision timing circuit comprises:
a quadrature clock block configured to select, from the plurality of fine phase signals, four fine phase signals that are quadrature shifted from each other for use as quadrature clock signals; and
a phase intersection block configured to:
receive the plurality of fine phase signals;
receive the quadrature clock signals;
receive a programmable target state signal identifying a target feedback divider state included in the plurality of feedback divider states;
receive a programmable target fine phase signal identifying a target fine phase sign

Assignees

• Hi Llc

Inventors

• Dahle Jacob
• Do Valle Bruno
• Jin Rong
• Field Ryan
• Sorgenfrei Sebastian

Classifications

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/0805

  the loop being adapted to provide an additional control signal for use outside the loop · CPC title

• H03L7/0996 Primary

  Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator · CPC title