Solid-state circuit breaker and breaking method for solid-state circuit breaker

Patent metadata

Field	Value
Publication number	US-11245255-B2
Application number	US-201816973098-A
Country	US
Kind code	B2
Filing date	Jun 11, 2018
Priority date	Jun 11, 2018
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A solid-state circuit breaker and breaking method are disclosed. In an embodiment, the solid-state circuit breaker includes a semiconductor switch; a controller, connected to the semiconductor switch; and an energy absorber, connected in parallel with the semiconductor switch. The controller is configured to obtain an equivalent inductance of a circuit of the solid-state circuit breaker upon a fault occurring in a line. Further, upon the equivalent inductance being greater than an inductance estimated value, the controller is configured to set a second current fault threshold. Finally, upon a fault current of the line reaching the second current fault threshold, the semiconductor switch is controlled to execute a closing operation.

First claim

The invention claimed is:

1. A solid-state circuit breaker, comprising:
a semiconductor switch;
a controller, connected to the semiconductor switch; and
an energy absorber, connected in parallel with the semiconductor switch,
wherein the controller is configured to obtain an equivalent inductance of a circuit of the solid-state circuit breaker upon a fault occurring in a line,
wherein, upon the equivalent inductance being greater than an inductance estimated value, the controller is configured to set a second current fault threshold; and
wherein, upon a fault current of the line reaching the second current fault threshold, the semiconductor switch is controlled to execute a closing operation.

2. The solid-state circuit breaker of claim 1 , wherein the semiconductor switch is a CMOS switch including,
a first NMOS transistor and a second NMOS transistor, a source of the first NMOS transistor and a source of the second NMOS transistor being connected together,
wherein the controller is separately connected to gates of the first NMOS transistor and the second NMOS transistor.

3. The solid-state circuit breaker of claim 2 , wherein the equivalent inductance is:

L
practicalseries

=

V
bus

di
dt

⁢

|

t
=

t
0

wherein V bus is a voltage of the line, i is a measured value of a line current, and t 0 is the time point when the fault occurs in the line.

4. The solid-state circuit breaker of claim 3 , wherein the second current fault threshold is:

I
newthrehold

=

Δ
⁢

⁢
T
×

V
clamp

-

V
bus

L
practicalseries

wherein V clamp is a clamping voltage, and ΔT is a fault disappearance time.

5. The solid-state circuit breaker of claim 4 , wherein an initial current fault threshold of the line is:

I
oldthrehold

=

V
clamp

-

V
bus

L
practicalseries

wherein I newthrehold <I oldthrehold .

6. The solid-state circuit breaker of claim 5 , wherein energy consumed by the energy absorber is:

E
TVS

=

∫

t
1

t
2

⁢

P
TVS

⁡

(
τ
)

⁢
d
⁢

⁢
τ

=

1
2

×

V
clamp

×
Δ
⁢

⁢
T

wherein P TVS (τ) is the instantaneous power at time point τ, E TVS <½×I oldthrehold ×V clamp ×ΔT.

7. The solid-state circuit breaker of claim 1 , wherein the energy absorber is a transient voltage suppression diode.

8. A breaking method for a solid-state circuit breaker, the solid-state circuit breaker including a semiconductor switch, a controller, connected to the semiconductor switch, an energy absorber, connected in parallel with the semiconductor switch, the breaking method comprising:
obtaining, via the controller, an equivalent inductance of a circuit of the solid-state circuit breaker upon a fault occurring in a line;
setting, via the controller, a second current fault threshold upon the equivalent inductance being greater than an inductance estimated value; and
controlling, upon a fault current of the line reaching the second current fault threshold, the semiconductor switch to execute a closing operation.

9. The breaking method for a solid-state circuit breaker of claim 8 , wherein the semiconductor switch is a CMOS switch including a first NMOS transistor and a second NMOS transistor; respective sources of the first NMOS transistor and the second NMOS transistor being connected together, is the controller being separately connected to respective gates of the first NMOS transistor and the second NMOS transistor.

10. The breaking method for a solid-state circuit breaker of claim 9 , wherein the equivalent inductance is:

L
practicalseries

=

V
bus

di
dt

⁢

|

t
=

t
0

wherein V bus is a voltage of the line, i is a measured value of a line current, and t 0 is the time point when the fault occurs in the line.

11. The breaking method for a solid-state circuit breaker of claim 10 , wherein the second current faul

Assignees

• Siemens Ag
• Du Feng
• Chen wei gang
• Zhuo Yue

Inventors

• Du Feng
• Chen wei gang
• Zhuo Yue

Classifications

• H02H3/087 Primary

  for DC applications · CPC title

• H02H9/02

  responsive to excess current {(current limitation for voltage regulators G05F1/573; disconnection after limiting H02H3/025)} · CPC title

• H02H9/025 Primary

  Current limitation using field effect transistors · CPC title

• H02H3/08

  responsive to excess current (responsive to abnormal temperature caused by excess current H02H5/04) · CPC title

• H02H9/021

  Current limitation using saturable reactors (H02H9/023 takes precedence) · CPC title