Semiconductor device, inverter circuit, drive device, vehicle, and elevator

Patent metadata

Field	Value
Publication number	US-11245017-B2
Application number	US-202016791576-A
Country	US
Kind code	B2
Filing date	Feb 14, 2020
Priority date	Aug 2, 2019
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A semiconductor device of an embodiment includes a first electrode, a second electrode, a silicon carbide layer between the first electrode and the second electrode, and the silicon carbide layer having a first plane and a second plane, the silicon carbide layer including a first trench, p-type first silicon carbide regions and n-type second silicon carbide regions alternately disposed, a p-type third silicon carbide region between the second silicon carbide region and the first plane, and an n-type fourth silicon carbide region between the third silicon carbide region and the first plane, and a p-type fifth silicon carbide region between the first silicon carbide region and the first trench, a gate electrode in the first trench, and a gate insulating layer. The length of the first silicon carbide region perpendicular to the first plane is longer than a depth of the first trench.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first electrode;
a second electrode;
a silicon carbide layer positioned between the first electrode and the second electrode, the silicon carbide layer having a first plane parallel to a first direction and a second direction intersecting the first direction, and a second plane parallel to the first direction and the second direction, the second plane facing the first plane, and the silicon carbide layer including:
a first trench positioned on a first plane side, the first trench extending in the first direction on the first plane;
first silicon carbide regions of p-type and second silicon carbide regions of n-type alternately disposed in the second direction;
a third silicon carbide region of p-type positioned between at least one of the second silicon carbide regions of n-type and the first plane;
a fourth silicon carbide region of n-type positioned between the third silicon carbide region of p-type and the first plane; and
a fifth silicon carbide region of p-type positioned between at least one of the first silicon carbide regions of p-type and the first trench, the fifth silicon carbide region of p-type having p-type impurity concentration higher than p-type impurity concentration of the at least one of the first silicon carbide regions of p-type;
a gate electrode positioned in the first trench; and
a gate insulating layer positioned between the gate electrode and the silicon carbide layer, wherein
a length of the at least one of the first silicon carbide regions of p-type in a third direction perpendicular to the first plane is longer than a depth of the first trench in the third direction.

2. The semiconductor device according to claim 1 , wherein an aspect ratio of the length of the at least one of the first silicon carbide regions of p-type in the third direction to a width of the at least one of the first silicon carbide regions of p-type in the second direction is 3 or more.

3. The semiconductor device according to claim 1 , wherein the length of the at least one of the first silicon carbide regions of p-type in the third direction is 3 μm or more.

4. The semiconductor device according to claim 1 , wherein a position shift amount of both ends of the at least one of the first silicon carbide regions of p-type in the second direction from both side planes of the first trench in the second direction is ±0.1 μm or less.

5. The semiconductor device according to claim 1 , wherein a position shift amount of both ends of the fifth silicon carbide region of p-type in the second direction from both side planes of the first trench in the second direction is ±0.1 μm or less.

6. The semiconductor device according to claim 1 , wherein the p-type impurity concentration of the fifth silicon carbide region of p-type is 10 times or more the p-type impurity concentration of the at least one of the first silicon carbide regions of p-type.

7. The semiconductor device according to claim 1 , wherein a relationship of a following expression is satisfied:
0.8≤( W 1× N 1)/( W 2× N 2)≤1.2

where W 1 is a width of the at least one of the first silicon carbide regions of p-type in the second direction, N 1 is the p-type impurity concentration of the at least one of the first silicon carbide regions of p-type, W 2 is a width of the at least one of the second silicon carbide regions of n-type in the second direction, and N 2 is n-type impurity concentration of the at least one of the second silicon carbide regions of n-type.

8. The semiconductor device according to claim 1 , wherein the p-type impurity concentration of the at least one of the first silicon carbide regions of p-type is 5×10 15 cm −3 or more and 5×10 17 cm −3 or less, and n-type impurity concentration of the at least one of the second silicon carbide regions of n-type is 5×10 15 cm −3 or more and 5×10 17 cm −3 or less.

9. The semiconductor device according to claim 1 , wherein
the silicon carbide layer further includes:
a second trench positioned on the first plane side, the second trench extending in the first direction on the first plane; and
a sixth silicon carbide region of p-type positioned between the second trench and another one of the first silicon carbide regions of p-type adjacent to the at least one of the first silicon carbide regions of p-type, the sixth silicon carbide region of p-type having p-type impurity concentration higher than the p-type impurity concentration of the another one of the first silicon carbide regions of p-type, and
a part of the first electrode is positioned in the second trench.

10. The semiconductor device according to claim 9 , wherein a distance between the second plane and the sixth silicon carbide region of p-type is smaller than a distance between the second plane and the fifth silicon carbide region of p-type.

11. The semiconductor device according to claim 9 , wherein a part of a junction between the part of the first electrode and the silicon carbide layer is a Schottky junction.

12. The semiconductor device according to claim 1 , wherein the silicon carbide layer includes a sixth silicon carbide region of n-type positioned between the at least one of the second silicon carbide regions of n-type and the third silicon carbide region of p-type, and the seventh sixth silicon carbide region of n-type has n-type impurity concentration higher than n-type impurity concentration of the at least one of the second silicon carbide regions of n-type.

13. The semiconductor device according to claim 1 , wherein the silicon carbide layer includes a sixth silicon carbide region of n-type positioned between the second plane and the at least one of the first silicon carbide regions of p-type and between the second plane and the at least one of the second silicon carbide regions of n-type, the sixth silicon carbide region of n-type has n-type impurity concentration lower than n-type impurity concentration of the at least one of the second silicon carbide regions of n-type.

14. The semiconductor device according to claim 1 , wherein the silicon carbide layer includes a sixth silicon carbide region of n-type positioned between the second plane and the at least one of the first silicon carbide regions of p-type and between the second plane and the at least one of the second silicon carbide regions of n-type, the sixth silicon carbide region of n-type has n-type impurity concentration higher than n-type impurity concentration of the at least one of the second silicon carbide regions of n-type, and the at least one of the first silicon carbide region of p-type is in contact with the sixth silicon carbide region of n-type.

15. An inverter circuit comprising the semiconductor device according to claim 1 .

16. A drive device comprising the semiconductor device according to claim 1 .

17. A vehicle comprising the semiconductor device according to claim 1 .

18. An elevator comprising the semiconductor device according to claim 1 .

Assignees

• Toshiba Kk

Inventors

• Kyogoku Shinya
• Nishio Johji
• Iijima Ryosuke

Classifications

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/307

  the doping variations being parallel to the channel lengths · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title