Thin film transistor and manufacturing method therefor, array substrate and display device

Patent metadata

Field	Value
Publication number	US-11244965-B2
Application number	US-201916768232-A
Country	US
Kind code	B2
Filing date	Oct 25, 2019
Priority date	Oct 29, 2018
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A thin film transistor, comprising a substrate, an active layer disposed on the substrate, and a source and drain that make electrical contact with the active layer, wherein the source and drain each comprise a first sub-electrode and a second sub-electrode that are stacked along a thickness of the active layer, and the first sub-electrode is closer to the active layer relative to the second sub-electrode. An area of an overlapping region between an orthographic projection of the second sub-electrode of at least one of the source and drain on the substrate and an overlapping region between an orthographic projection of the first sub-electrode of the at least one of the source and the drain on the substrate and the orthographic projection of the active layer on the substrate.

First claim

What is claimed is:

1. A thin film transistor, comprising a substrate, an active layer disposed on the substrate, and a source and a drain that are in electrical contact with the active layer, wherein the source and the drain each include a first sub-electrode and a second sub-electrode that are stacked along a thickness of the active layer, and the first sub-electrode is closer to the active layer relative to the second sub-electrode; and
an area of an overlapping region between an orthographic projection of the second sub-electrode of at least one of the source and the drain on the substrate and an orthographic projection of the active layer on the substrate is less than an area of an overlapping region between an orthographic projection of the first sub-electrode of the at least one of the source and the drain on the substrate and the orthographic projection of the active layer on the substrate;
the active layer includes: a first contact portion in electrical contact with the first sub-electrode of the source, a second contact portion in electrical contact with the first sub-electrode of the drain and a non-contact portion located between the first contact portion and the second contact portion;
a distance, in a first direction, between an edge of the second sub-electrode of the source proximate to the non-contact portion and an edge of the second sub-electrode of the drain proximate to the non-contact portion is greater than a length of the non-contact portion in the first direction;
the first direction is a direction parallel to the substrate and pointing to the second contact portion from the first contact portion;
a distance, in the first direction, from an edge of the second sub-electrode of the at least one of the source and the drain proximate to the non-contact portion to an edge of the non-contact portion proximate to the second sub-electrode of the at least one of the source and the drain is 2 μm to 7 μm;
a distance, in the first direction, from the edge of the second sub-electrode of at least one of the source and the drain proximate to the non-contact portion to the edge of the non-contact portion proximate to the second sub-electrode of the at least one of the source and the drain is greater than or equal to a length of a corresponding contact portion in the first direction, wherein
the corresponding contact portion is a contact portion of the first contact portion and the second contact portion closest to the second sub-electrode.

2. The thin film transistor according to claim 1 , wherein a distance, in the first direction, from any position on the edge of the second sub-electrode of the at least one of the source and the drain proximate to the non-contact portion to the edge of the non-contact portion proximate to the second sub-electrode of the at least one of the source and the drain is equal.

3. The thin film transistor according to claim 2 , wherein in a case where in the first direction, the distance from any position on the edge of the second sub-electrode of the source proximate to the non-contact portion to an edge of the non-contact portion proximate to the second sub-electrode of the source is equal, and the distance from any position on the edge of the second sub-electrode of the drain proximate to the non-contact portion to an edge of the non-contact portion proximate to the second sub-electrode of the drain is equal,
in the first direction, the distance from the edge of the second sub-electrode of the source proximate to the non-contact portion to the edge of the non-contact portion proximate to the second sub-electrode of the source is equal to the distance from the edge of the second sub-electrode of the drain proximate to the non-contact portion to the edge of the non-contact portion proximate to the second sub-electrode of the drain.

4. The thin film transistor according to claim 1 , wherein the second sub-electrode of the at least one of the source and the drain has at least one hollow-out region, and an orthographic projection of the at least one hollow-out region on the substrate is within a range of the orthographic projection of the active layer on the substrate.

5. The thin film transistor according to claim 1 , wherein the thin film transistor further comprises a gate and a gate insulating layer, along a direction pointing to the active layer from the substrate, the gate and the gate insulating layer are sequentially disposed between the substrate and the active layer.

6. The thin film transistor according to claim 1 , wherein a material of the second sub-electrode includes at least one of copper, aluminum and silver.

7. An array substrate, comprising the thin film transistor according to claim 1 .

8. A display device, comprising the array substrate according to claim 7 .

9. A method for manufacturing a thin film transistor, the method comprising:
forming an active layer above a substrate; and
forming a source and a drain on the substrate above which the active layer has been formed, wherein
the source and the drain are separately in electrical contact with the active layer; the source and the drain each include a first sub-electrode and a second sub-electrode that are stacked along a thickness of the active layer, and the first sub-electrode is closer to the active layer relative to the second sub-electrode;
an area of an overlapping region between an orthographic projection of the second sub-electrode of at least one of the source and the drain and an orthographic projection of the active layer on the substrate is less than an area of an overlapping region between an orthographic projection of the first sub-electrode of the at least one of the source and the drain and the orthographic projection of the active layer on the substrates;
the active layer includes: a first contact portion in electrical contact with the first sub-electrode of the source, a second contact portion in electrical contact with the first sub-electrode of the drain and a non-contact portion located between the first contact portion and the second contact portion;
a distance, in a first direction, from an edge of the second sub-electrode of at least one of the source and the drain proximate to the non-contact portion to an edge of the non-contact portion proximate to the second sub-electrode of the at least one of the source and the drain is greater than or equal to a length of a corresponding contact portion in the first direction, wherein
the first direction is a direction parallel to the substrate and pointing to the second contact portion from the first contact portion;
the corresponding contact portion is a contact portion of the first contact portion and the second contact portion closest to the second sub-electrode;
forming the source and the drain on the substrate above which the active layer has been formed includes:
sequentially forming a first conductive layer and a second conductive layer on the substrate above which the active layer has been formed;
patterning the first conductive layer and the second conductive layer through a first patterning process to form an initial source and an initial drain, wherein the initial source and the initial drain each include a first sub-electrode formed out of the first conductive layer and an initial second sub-electrode formed out of the second conductive layer;
forming an etch stop layer on the substrate on which the initial source and the initial drain have been formed;
grinding the etch stop layer though a grinding process, or patterning the etch stop layer through a second patterning process, so as to expose surfaces of portions, which overlap the active layer, of initial second sub-electrodes of the initial source and the initial drain; and
etching the initia

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Cao Binbin

Classifications

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/427

  having different thicknesses of the semiconductor bodies in different TFTs · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D30/6729 Primary

  characterised by the electrodes · CPC title

• H10D30/6713 Primary

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title