Array of capacitors, array of memory cells, methods of forming an array of capacitors, and methods of forming an array of memory cells

Patent metadata

Field	Value
Publication number	US-11244952-B2
Application number	US-201816225814-A
Country	US
Kind code	B2
Filing date	Dec 19, 2018
Priority date	Dec 19, 2018
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A method of forming an array of capacitors comprises forming a plurality of horizontally-spaced groups that individually comprise a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another. A horizontally-elongated conductive line is formed atop and is directly electrically coupled to the upper capacitor electrode material in individual of the groups. Other methods, including structure independent of method of manufacture, are disclosed.

First claim

The invention claimed is:

1. A method of forming an array of capacitors, comprising:
forming a plurality of horizontally-spaced groups individually comprising a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover, adjacent of the groups being horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups, an unfilled void space being between the adjacent groups, the unfilled void space comprising at least a portion thereof that is below tops of the lower capacitor electrodes;
forming upper capacitor electrode material in the portion of the void space that is below the tops of the lower capacitor electrodes and in the groups over the capacitor insulator and the lower capacitor electrodes, the upper capacitor electrode material in the void space connecting the upper capacitor electrode material that is in the adjacent groups relative to one another, the upper capacitor electrode material less-than-filling the portion of the void space that is below the tops of the lower capacitor electrodes;
removing at least a portion of the upper capacitor electrode material from the portion of the void space that is below the tops of the lower capacitor electrodes to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another; and
forming a horizontally-elongated conductive line atop and directly electrically coupled to the upper capacitor electrode material in individual of the groups.

2. The method of claim 1 wherein the upper capacitor electrode material has a thickness that is no more than one third of minimum horizontal width of the portion of the void space that is below the tops of the lower capacitor electrodes.

3. The method of claim 2 wherein the thickness is not more than one fourth of the minimum horizontal width.

4. The method of claim 3 wherein the thickness is not more than one fifth of the minimum horizontal width.

5. The method of claim 1 wherein the removing forms the upper capacitor electrode material as an upper capacitor electrode that is common to all capacitors within the individual groups; the capacitors within the individual groups individually comprising one of the lower capacitor electrodes, the capacitor insulator, and the common upper capacitor electrode in the respective individual group.

6. The method of claim 1 wherein the lower capacitor electrodes are pillars.

7. The method of claim 1 wherein,
the portion of the void space that is below the tops of the lower capacitor electrodes is horizontally-elongated in a column direction;
the lower capacitor electrodes in the individual groups are arrayed in horizontally-elongated rows in a row direction that is orthogonal to the column direction; and
the portion of the void space that is below the tops of the lower capacitor electrodes having a minimum width in the row direction that is at least two times maximum pitch of the lower capacitor electrodes in the row direction.

8. The method of claim 7 wherein the lower capacitor electrodes in the individual groups are arrayed in a 2D Bravais lattice.

9. The method of claim 8 wherein the lattice is rectangular or square.

10. The method of claim 1 wherein the capacitor insulator is ferroelectric.

11. The method of claim 1 comprising forming the upper capacitor electrode material along sidewalls of the portion of the void space that is below the tops of the lower capacitor electrodes.

12. The method of claim 1 wherein the capacitor insulator extends laterally all across a base of the portion of the void space that is below the tops of the lower capacitor electrodes.

13. The method of claim 12 wherein the capacitor insulator has a thickness that is less than a horizontal thickness of individual of the lower capacitor electrodes.

14. A method of forming an array of capacitors, comprising:
forming a plurality of horizontally-spaced groups individually comprising a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover, adjacent of the groups being horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups, a void space being between the adjacent groups;
forming upper capacitor electrode material in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes, the upper capacitor electrode material in the void space connecting the upper capacitor electrode material that is in the adjacent groups relative to one another, the upper capacitor electrode material less-than-filling the void space;
removing at least a portion of the upper capacitor electrode material from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another;
forming a horizontally-elongated conductive line atop and directly electrically coupled to the upper capacitor electrode material in individual of the groups; and
the removing comprising anisotropic etching that is maskless over the groups and the void space.

15. The method of claim 14 wherein,
the capacitor insulator extends laterally across a base of the void space;
the upper capacitor electrode material is formed atop that portion of the capacitor insulator that extends laterally across the base of the void space; and
the maskless anisotropic etching removes the upper capacitor electrode material from being over a central part of that portion of the capacitor insulator that extends laterally across the base of the void space.

16. The method of claim 15 comprising forming the upper capacitor electrode material along sidewalls of the void space, the maskless anisotropic etching leaving that part of the upper capacitor electrode material that is along sidewalls of the void space directly above remaining opposing non-central parts of that portion of the capacitor insulator that extends laterally across the base of the void space.

17. The method of claim 1 comprising forming a plurality of transistors that individually directly electrically couple to individual of the lower capacitor electrodes.

18. The method of claim 17 wherein the transistors are vertical transistors.

19. The method of claim 1 comprising forming the horizontally-elongated conductive line directly against the capacitor insulator and directly against the upper capacitor electrode material in the individual groups.

20. A method of forming an array of capacitors, comprising:
forming a plurality of horizontally-spaced groups individually comprising a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover, adjacent of the groups being horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups, a void space being between the adjacent groups;
forming upper capacitor electrode material in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes, the upper capacitor electrode material in the void space connecting the upper capacitor electrode material that is in the adjacent groups relative to one another, the upper capacitor electrode material less-than-filling the void space;
removing at least a portion of the upper capacitor electrode material from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another;
forming a horizontally-elongated conductive line atop and dir

Assignees

• Micron Technology Inc

Inventors

• Chhajed Sameer
• Chavan Ashonita A
• Fischer Mark
• Ramaswamy Durai Vishak Nirmal

Classifications

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/692 Primary

  Electrodes · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title