Integrated duplex deployment function with safety diagnostics for restraint control module

Patent metadata

Field	Value
Publication number	US-11239835-B2
Application number	US-201916512917-A
Country	US
Kind code	B2
Filing date	Jul 16, 2019
Priority date	Jul 16, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

An active power blocking circuit in series with a squib. The active power blocking circuit may include a logic circuit, a first switch, a second switch, and an amplifier. The first switch may have a first side connected to a positive connection and a second side connected to a negative connection. The second switch may have a first side connected to the positive connection and a second side connected to the negative connection through a diode. The amplifier may be connected the second side of the second switch and the output of the amplifier may be connected to the logic circuit.

First claim

The invention claimed is:

1. An active power blocking circuit in series with a squib, the active power blocking circuit comprising:
a logic circuit;
a first switch having a first side connected to a positive connection and a second side connected to a negative connection;
a second switch having a first side connected to the positive connection and a second side connected to the negative connection through a diode; and
an amplifier connected the second side of the second switch, an output of the amplifier being connected to the logic circuit.

2. The active power blocking circuit of claim 1 , wherein the first switch is comprised of a first transistor and a second transistor.

3. The active power blocking circuit of claim 2 , wherein the first transistor having a drain connected to the positive connection and a source connected to a source of the second transistor, the drain of the second transistor being connected to the negative connection.

4. The active power blocking circuit of claim 3 , wherein the source of the first transistor and the source of the second transistor are connected to the amplifier.

5. The active power blocking circuit of claim 2 , wherein the second switch is a third transistor, a drain of the third transistor being connected to the positive connection, a source of the third transistor being connected to the negative connection through the second transistor.

6. The active power blocking circuit of claim 5 , wherein a drain of third transistor is connected to the positive connection and a source of the third transistor is connected to a source of the second transistor through a first resistor, the drain of the second transistor being connected to the negative connection.

7. The active power blocking circuit of claim 6 , wherein the source of the third transistor is connected to the amplifier through a second resistor.

8. The active power blocking circuit of claim 1 , further comprising a reverse sensing amplifier having a negative input connected to squib monitoring connection and a positive input connected to a voltage source.

9. The active power blocking circuit of claim 1 , further comprising a third switch having a first side connected to the positive connection and a second side connected to the negative connection through a diode, the second side of the third switch being connected to the amplifier.

10. The active power blocking circuit of claim 1 , further comprising a power storage device in communication with the positive connection.

11. The active power blocking circuit of claim 10 , wherein the power storage device comprises a capacitor and a diode, an anode of the diode being connected to the positive connection, a cathode of the diode being connected to the capacitor.

12. A duplex restraint module, the duplex restraint module comprising:
a first squib;
a first active power blocking circuit in series with the first squib, the first active power blocking circuit comprising a logic circuit, a first switch, a second switch and an amplifier, the first switch having a first side connected to a positive connection and a second side connected to a negative connection, the second switch having a first side connected to the positive connection and a second side connected to the negative connection through a diode, an amplifier connected the second side of the second switch, an output of the amplifier being connected to the logic circuit;
a second squib; and
a second active power blocking circuit in series with the second squib, the second active power blocking circuit comprising a logic circuit, a first switch, a second switch and an amplifier, the first switch having a first side connected to a positive connection and a second side connected to a negative connection, the second switch having a first side connected to the positive connection and a second side connected to the negative connection through a diode, an amplifier connected the second side of the second switch, an output of the amplifier being connected to the logic circuit.

13. The duplex restraint module of claim 12 , wherein a first side of the first squib is connected to the positive connection of the first active power blocking circuit and a second side of the first squib is connected to the negative connection of the second active blocking circuit.

14. The duplex restraint module of claim 13 , wherein a first side of the second squib is connected to the positive connection of the second active power blocking circuit and a second side of the second squib is connected to the negative connection of the first active blocking circuit.

15. The duplex restraint module of claim 14 , wherein a capacitor is connected between the second side of the first squib and the second side of the second squib.

16. An active power blocking circuit in series with a squib, the active power blocking circuit comprising:
a logic circuit having an active state and a first sensing state;
a first switch having a first side connected to a positive connection and a second side connected to a negative connection, the first switch conducting in the active state;
a second switch having a first side connected to the positive connection and a second side connected to the negative connection through a diode, the second switch conducting in the first sensing state; and
an amplifier connected the second side of the second switch, an output of the amplifier being connected to the logic circuit.

17. The active power blocking circuit of claim 16 , wherein logic circuit is configured to measure the output of the amplifier in the first sensing state.

18. The active power blocking circuit of claim 16 , further comprising a third switch having a first side connected to the positive connection and a second side connected to the negative connection through the diode, the third switch conducting in a second sensing state of the logic circuit.

19. The active power blocking circuit of claim 18 , wherein the logic circuit is configured to measure the output of the amplifier in the first sensing state.

20. The active power blocking circuit of claim 16 , wherein the logic circuit is configured to transition from the active state to the first sensing state based on a timer.

21. An active power blocking circuit in series with a squib, the active power blocking circuit comprising:
a logic circuit;
a first switch having a first side connected to a positive connection and a second side connected to a negative connection;
a second switch having a first side connected to the positive connection and a second side connected to the negative connection through a diode; and
a third switch having a first side connected to the positive connection and a second side connected to the negative connection through a diode;
a first amplifier having a positive input connected to the second side of the third switch and a negative input connected to an internal reference voltage, and an output of the first amplifier being connected to the logic circuit; and
a second amplifier having a negative input connected a squib monitoring input and a positive input connected to an internal reference voltage, and an output of the second amplifier being connected to the logic circuit.

Assignees

• Veoneer Us Inc

Inventors

• Eiswerth David
• Colarossi Vincent
• Liedtke Marco
• Budde Wolfram

Classifications

• H03K17/74

  by the use, as active elements, of diodes (by the use of more than one type of semiconductor device H03K17/567; by the use of tunnel diodes H03K17/58; by the use of negative resistance diodes H03K17/70) · CPC title

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• F42D1/05

  Electric circuits for blasting · CPC title

• H03K19/007 Primary

  Fail-safe circuits · CPC title

• B60R21/26

  characterised by the inflation fluid source or means to control inflation fluid flow {(arrangement or mounting thereof to the vehicle B60R21/20; blasting cartridges for producing gas under pressure in general F42B3/04; initiators or igniters therefor F42B3/10)} · CPC title