Structure of memory device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-11239419-B2
Application number	US-201916505190-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Jun 5, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

The present invention relates to a structure of a memory device. The structure of a memory device includes a substrate, including a bottom electrode layer formed therein. A buffer layer is disposed on the substrate, in contact with the bottom electrode layer. A resistive layer surrounds a whole sidewall of the buffer layer, and extends upward vertically from the substrate. A mask layer is disposed on the buffer layer and the resistive layer. A noble metal layer is over the substrate, and fully covers the resistive layer and the mask layer. A top electrode layer is disposed on the noble metal layer.

First claim

What is claimed is:

1. A structure of memory device, comprising:
a substrate, comprising a bottom electrode layer therein;
a buffer layer, disposed on the substrate, in contact with the bottom electrode layer;
a resistive layer, surrounding a whole sidewall of the buffer layer and extending upward vertically from the substrate, wherein the bottom electrode layer contacts with the buffer layer but does not contact with the resistive layer;
a mask layer, disposed on the buffer layer and the resistive layer;
a noble metal layer, disposed over the substrate and fully covering sidewalls of the resistive layer and sidewalls and top of the mask layer; and
a top electrode layer, disposed on the noble metal layer.

2. The structure of memory device according to claim 1 , wherein the resistive layer comprises a transition metal oxide layer.

3. The structure of memory device according to claim 2 , wherein the buffer layer is an oxygen trap layer.

4. The structure of memory device according to claim 3 , wherein the buffer layer comprises Hf, HfOx, Ta, TaOx, NiOx, TiOx, ZrOx, or ZnOx.

5. The structure of memory device according to claim 2 , wherein an oxygen content of the transition metal oxide layer is in a saturation state.

6. The structure of memory device according to claim 1 , wherein a size of the resistive layer is determined by a horizontal thickness of the resistive layer and a thickness of the buffer layer.

7. The structure of memory device according to claim 1 , wherein the noble metal layer reduces oxygen diffused into or away from the resistive layer.

8. The structure of memory device according to claim 1 , wherein the top electrode layer is thicker than the noble metal layer and a thickness of the noble metal layer is in a range of 30 to 50 angstroms.

9. The structure of memory device according to claim 1 , wherein the substrate comprises:
a base layer, comprising an interconnection line structure therein;
an inter-layer dielectric layer, disposed on the base layer and comprising an opening;
a through via structure, filling into a lower portion of the opening; and
the bottom electrode layer, filling into an upper portion of the opening.

10. The structure of memory device according to claim 1 , wherein the substrate comprises:
a base layer, comprising an interconnection line structure therein;
an inter-layer dielectric layer, disposed on the base layer and comprising an opening;
a through via structure, filling into a lower portion of the opening; and
the bottom electrode layer, disposed on the inter-layer dielectric layer and above the through via structure,
wherein the noble metal layer and the bottom electrode layer are isolated at least by the resistive layer.

Assignees

• United Microelectronics Corp

Inventors

• Liu Hai Tao
• Ding Li Li
• Liu Yao-Hung
• Du Guoan
• Li qi lu
• Wan Chunlei
• Lin yi yu
• Chen Yuchao
• Li Huakai
• Chen Hung-Yueh

Classifications

• H01L45/124

  Electricity · mapped topic

• H01L45/1633

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/08

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic