Architecture for hybrid TFT-based micro display projector

Patent metadata

Field	Value
Publication number	US-11239399-B2
Application number	US-201916660643-A
Country	US
Kind code	B2
Filing date	Oct 22, 2019
Priority date	Feb 5, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

For small, high-resolution, light-emitting diode (LED) displays, such as for a near-eye display in an artificial-reality headset, LEDs are spaced closely together. A backplane can be used to drive an array of LEDs in an LED display. A plurality of interconnects electrically couple the backplane with the array of LEDs. As spacing between LEDs becomes smaller than interconnect spacing, a thin-film circuit layer can be used to reduce a number or interconnects between the backplane and the array of LEDs, so that interconnect spacing can be larger than LED spacing. This can allow LEDs in the LED display to be more densely arranged while still allowing use of a silicon backplane with drive circuitry to control operation of the LEDs in the LED display.

First claim

What is claimed is:

1. An apparatus comprising:
an array of light emitting diodes (LEDs) comprising a layered epitaxial structure including a first doped semiconductor layer, a second doped semiconductor layer, and a light-emitting layer between the first doped semiconductor layer and the second doped semiconductor layer;
a thin-film circuit layer deposited, rather than bonded using bonding pads, on the array of LEDs, wherein the array of LEDs is a support structure for the thin-film circuit layer, and the thin-film circuit layer comprises circuitry for controlling operation of LEDs in the array of LEDs; and
a backplane coupled with the thin-film circuit layer using a plurality of metal bonds between the backplane and the thin-film circuit layer, the backplane comprising drive circuitry for supplying electrical current to the thin-film circuit layer through the plurality of metal bonds, wherein the number of metal bonds in the plurality of metal bonds is less than the number of LEDs in the array of LEDs.

2. The apparatus of claim 1 , wherein:
the array of LEDs has a light-emitting side and a side opposite the light-emitting side, and the thin-film circuit layer is deposited on the side opposite the light-emitting side of the array of LEDs; and
the thin-film circuit layer comprises transistors and capacitors interconnected to form pixel circuits for controlling operation of LEDs in the array of LEDs.

3. The apparatus of claim 2 , wherein the pixel circuits implement analog, pulse-code modulation, or pulse-width modulation for controlling intensity of LEDs in the array of LEDs.

4. The apparatus of claim 2 , wherein a storage capacitor of a pixel circuit is configured to be coupled to a dateline by one or more selection signals.

5. The apparatus of claim 2 , wherein pixel circuits are interconnected to reduce a number of metal bonds between the backplane and the thin-film circuit layer.

6. The apparatus of claim 1 , wherein a single pixel circuit is connected to multiple row selection signals.

7. The apparatus of claim 1 , wherein the backplane is configured to transmit a global signal, through a metal bond of the plurality of metal bonds, to the thin-film circuit layer, wherein the global signal comprises one or more of a row dataline, a column dataline, an analog bias, a voltage supply, a pulse clocks, or test enablement features.

8. The apparatus of claim 1 , wherein no transistor in the thin-film circuit layer is used to drive a global net.

9. The apparatus of claim 1 , wherein the thin-film circuit layer comprises a selector multiplexor.

10. The apparatus of claim 9 , wherein:
the selector multiplexor comprises a common signal line in the thin-film circuit layer electrically coupled with a plurality of transistors in the thin-film circuit layer; and
the plurality of transistors are configured to alternate activation so that current from the common signal line is periodically passed through each of the plurality of transistors.

11. The apparatus of claim 1 , wherein the thin-film circuit layer comprises memory circuits and modulator circuits.

12. The apparatus of claim 1 , wherein:
a unique address is assigned to each LED in the array of LEDs; and
a control signal comprises the unique address and an operation signal to control operation of a selected LED in the array of LEDs.

13. The apparatus of claim 12 , wherein:
the operation signal is configured to control a magnitude of current that flows through the selected LED; and
the operation signal comprises a digital signal representing a percentage of a time within a time period for which current flows to the selected LED.

14. The apparatus of claim 1 , wherein spacing between centers of LEDs are spaced no further apart than three microns.

15. A method comprising:
obtaining a semiconductor structure, wherein the semiconductor structure is a layered epitaxial structure including a first doped semiconductor layer, a second doped semiconductor layer, and a light-emitting layer between the first doped semiconductor layer and the second doped semiconductor layer;
depositing, rather than bonding using bonding pads, a thin-film circuit layer on the semiconductor structure;
forming circuitry in the thin-film circuit layer for controlling light emission from the light-emitting layer;
obtaining a backplane, the backplane comprising drive circuitry for supplying electrical current to the thin-film circuit layer through a plurality of metal bonds between the backplane and the thin-film circuit layer;
forming a plurality of interconnects on the thin-film circuit layer or on the backplane;
bonding the backplane to the thin-film circuit layer using the plurality of interconnects, wherein the plurality of interconnects become the plurality of metal bonds after bonding; and
forming an array of light emitting diodes (LEDs) from the semiconductor structure, wherein the number of metal bonds in the plurality of metal bonds is less than the number of LEDs in the array of LEDs, the array of LEDs have a light-emitting side and a side opposite the light-emitting side, and wherein the thin-film circuit layer is deposited on the side opposite the light-emitting side.

16. The method of claim 15 , wherein obtaining the backplane comprises forming a plurality of CMOS transistors and the plurality of interconnects in a silicon device layer of a silicon wafer.

17. The method of claim 15 , wherein forming the array of LEDs comprises singulating the semiconductor structure, and wherein singulating the semiconductor structure occurs before bonding the backplane to the thin-film circuit layer.

18. The method of claim 15 , wherein the thin-film circuit layer is formed on the semiconductor structure on a wafer level.

19. The method of claim 15 , wherein the backplane includes electrical circuits formed in the backplane before bonding.

20. A system for a near-eye display, the system comprising:
a frame;
a waveguide display coupled with the frame; and
a projector comprising a light source, the projector configured to direct light to the waveguide display, wherein the light source comprises:
an array of light emitting diodes (LEDs) comprising a layered epitaxial structure including a first doped semiconductor layer, a second doped semiconductor layer, and a light-emitting layer between the first doped semiconductor layer and the second doped semiconductor layer;
a thin-film circuit layer deposited, rather than bonded using bonding pads, on the array of LEDs, wherein the array of LEDs is a support structure for the thin-film circuit layer, and the thin-film circuit layer comprises circuitry for controlling operation of LEDs in the array of LEDs; and
a backplane coupled with the thin-film circuit layer using a plurality of metal bonds between the backplane and the thin-film circuit layer, the backplane comprising drive circuitry for supplying electrical current to the thin-film circuit layer through the plurality of metal bonds, wherein the number of metal bonds in the plurality of metal bonds is less than the number of LEDs in the array of LEDs.

Assignees

• Facebook Tech Llc

Inventors

• Morris Daniel Henry
• Goward John
• Fabien Chloe Astrid Marie
• Grundmann Michael

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/072

  of bump connectors · CPC title