CMOS color image sensors with metamaterial color splitting

Patent metadata

Field	Value
Publication number	US-11239276-B2
Application number	US-201916657640-A
Country	US
Kind code	B2
Filing date	Oct 18, 2019
Priority date	Oct 18, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

Methods to build multi-functional scattering structures while respecting tight requirements imposed by manufacturing processes are described. The described methods and devices are based on etching away wire networks embedded in 3D structures to form voids in order to perform a target function. Optimization algorithms for designing binarized devices that meet manufacturing requirements are also disclosed.

First claim

What is claimed is:

1. A method for building a three-dimensional (3D) scattering structure, comprising:
forming a dielectric structure comprising a first dielectric and a network of metal wires, wherein location, shape and size of the metal wires are selected according to one or more target functions; and
etching away the metal wires from the dielectric structure, thus forming a structure containing spaces filled with the first dielectric and voids, wherein location, shape and size of the voids is according to the one or more target functions,
wherein the thus formed 3D light scattering structure is configured to receive electromagnetic waves and scatter the electromagnetic waves in accordance with the one or more target functions.

2. The method of claim 1 , further comprising filling the voids with a second dielectric different from the first dielectric, thus obtaining a 3D light scattering structure made of two different dielectrics.

3. The method of claim 1 , wherein the etching is performed by generating vias in the 3D scattering structure.

4. The method of claim 1 , wherein the forming is performed through a CMOS process.

5. The method of claim 2 , wherein the first and the second dielectric materials comprise SiCOH and TiO2 respectively.

6. The method of claim 1 , wherein the forming is performed using stacked layers.

7. The method of claim 6 , wherein the location and size of the voids are provided using an optimization method based on gradient descent.

8. The method of claim 7 , wherein the voids within each layer have geometric shapes each represented by one or more parameters.

9. The method of claim 8 , wherein each geometric shape is a rectangle and the one or more parameters comprise a center and two widths along horizontal directions.

10. The method of claim 9 , wherein the optimization method comprises providing an initial 3D pattern using a continuous optimization algorithm to generate a refractive index distribution along horizontal directions within each layer.

11. The method of claim 10 , wherein the optimization method further comprises:
for each layer:
identifying minima of the refractive index distribution to provide the location of voids; based on the continuous optimization algorithm, ranking voids to indicate how binarized each void is;
proceeding from a highest ranked to a lowest ranked void, setting the two widths and the center for each void;
checking each void against a set size and a set pitch requirement to provide a set of acceptable voids; and
perturbing the two widths of voids of the set of acceptable voids based on the continuous optimization algorithm to further optimize and improve overall performance of the 3D scattering structure.

12. The method of claim 11 , wherein the set size and pitch requirements are related to CMOS manufacturing constraints.

13. An image sensor built based on the method of claim 1 .

Assignees

• California Inst Of Techn

Inventors

• Roberts Gregory
• Camayd-Munoz Philip
• Ballew Conner
• Faraon Andrei

Classifications

• H10F39/806

  Optical elements or arrangements associated with the image sensors · CPC title

• H10F77/40

  Optical elements or arrangements (surface textures H10F77/70) · CPC title

• H10F39/8053 Primary

  Colour filters · CPC title

• H10F39/8027

  Geometry of the photosensitive area · CPC title

• H10F39/8023

  Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery · CPC title