Control signal generator and driving method thereof

Patent metadata

Field	Value
Publication number	US-11238910-B2
Application number	US-202016834667-A
Country	US
Kind code	B2
Filing date	Mar 30, 2020
Priority date	Oct 28, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A signal generator includes N stages of cascaded control signal generating circuits, and is configured to receive K clock signals whose valid pulse edges are different from each other by a set time, an n-th control signal generating circuit of the N stages of control signal generating circuit generates a strobe signal based on a k-th clock signal of the K clock signals and sequentially outputs at least two different clock signals of other K−1 clock signals based on the strobe signal. A valid pulse edge of the k-th clock signal is within a valid pulse duration of a strobe signal of an (n−1)-th stage control signal generating circuit.

First claim

We claim:

1. A control signal generator comprising N stages of cascaded control signal generating circuits and configured to receive K clock signals whose valid pulse edges are different from each other by a set time, wherein an n-th control signal generating circuit of the N stages of control signal generating circuit is configured to:
generate a strobe signal based on a k-th clock signal of the K clock signals; and
sequentially output at least two different clock signals of other K−1 clock signals of the K clock signals as control signals based on the strobe signal;
wherein a valid pulse edge of the k-th clock signal is within a valid pulse duration of a strobe signal of an (n−1)-th stage control signal generating circuit; N is an integer greater than or equal to 1, n is greater than or equal to 1 and less than or equal to N, K is an integer greater than or equal to 3, and k is greater than or equal to 1 and less than or equal to K; and
wherein the strobe signal of the (n−1)-th stage control signal generating circuit is electrically connected to an input terminal the n-th stage control signal generating circuit.

2. The control signal generator according to claim 1 , wherein the n-th stage control signal generating circuit comprises:
a strobe sub-circuit having a first input terminal, a second input terminal and an output terminal, the first input terminal of the strobe sub-circuit being electrically connected to an output terminal of the strobe sub-circuit of the (n−1)-th stage control signal generating circuit, the second input terminal of the strobe sub-circuit being electrically connected to receive the k-th clock signal, and the output terminal of the strobe sub-circuit being electrically connected to first input terminals of at least two switching sub-circuits to provide the strobe signal;
the at least two switching sub-circuits, each having a first input terminal and a second input terminal, the second input terminals of each of the at least two switching sub-circuits being electrically connected to receive different clock signals of the other K−1 clock signals;
wherein the second input terminal of the strobe sub-circuit is also electrically connected to a second input terminal of a first switching sub-circuit of the at least two switching sub-circuits of the (n−1)-th stage control signal generating circuit, the first switching sub-circuit being a switching sub-circuit that outputs a control signal last of the at least two switching sub-circuits that sequentially output control signals.

3. The control signal generator according to claim 2 , wherein when N is greater than or equal to 3, the first input terminal of the strobe sub-circuit of a first stage control signal generating circuit is electrically connected to the output terminal of the strobe sub-circuit of an N-th stage control signal generating circuit.

4. The control signal generator according to claim 2 , wherein the strobe sub-circuit comprises a latch, a data input terminal of the latch is used as the first input terminal of the strobe sub-circuit, and a clock input terminal of the latch is used as the second input terminal of the strobe sub-circuit.

5. The control signal generator according to claim 2 , wherein each of the at least two switching sub-circuits comprises:
a transmission gate, a control terminal of the transmission gate being used as the first input terminal of the switching sub-circuit, and a data input terminal of the transmission gate being used as the second input terminal of the switching sub-circuit.

6. The control signal generator according to claim 1 , wherein valid pulse edges of the K clock signals are sequentially different by 1/K clock signal period, and a duty cycle of each of the K clock signals is 1/K.

7. A driving method for the control signal generator according to claim 1 , comprising:
applying K clock signals to the control signal generator; wherein
the n-th stage control signal generating circuit:
generates the strobe signal of the n-th stage control signal generating circuit based on the k-th clock signal of the K clock signals and the strobe signal of the (n−1)-th stage control signal generating circuit; and
sequentially outputs at least two different clock signals of the other K−1 clock signals as control signals based on the strobe signal of the n-th stage control signal generating circuit.

8. The driving method according to claim 7 , wherein a valid pulse edge of the k-th clock signal is within a valid pulse duration of the strobe signal of the (n−1)-th stage control signal generating circuit.

9. The driving method according to claim 7 , wherein in response to applying K clock signals whose valid pulse edges are different from each other by a set time to the control signal generator, an enable signal is also applied to a first stage control signal generating circuit, wherein a valid pulse edge of a clock signal based on which the first stage control signal generating circuit generates the strobe signal is within a valid pulse duration of the enable signal.

10. The driving method according to claim 7 , wherein valid pulse edges of the K clock signals are sequentially different by 1/K clock signal period, and a duty cycle of each of the K clock signals is 1/K.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Junrui
• Zhu Xuehui
• Lan Ronghua
• He Zongze
• Zhang Yehao

Classifications

• H03K5/15013

  with more than two outputs · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C7/1066

  Output synchronization · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title