Display module including electro-static discharge protection circuit

Patent metadata

Field	Value
Publication number	US-11238818-B2
Application number	US-202117154077-A
Country	US
Kind code	B2
Filing date	Jan 21, 2021
Priority date	Mar 27, 2018
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A display module including a plurality of pixels is provided. The display module according to an embodiment includes a plurality of inorganic light emitting elements constituting the plurality of pixels, a plurality of pixel circuits provided for each of the plurality of inorganic light emitting elements and providing a driving current corresponding to an applied grayscale data voltage to each of the plurality of inorganic light emitting elements, and an ESD (Electro Static Discharge) protection circuit arranged in at least one of the plurality of pixel circuits.

First claim

What is claimed is:

1. A display module comprising:
a substrate;
a thin film transistor (TFT) layer formed on the substrate; and
a plurality of pixels disposed on the TFT layer,
wherein each pixel of the plurality of pixels comprises at least three inorganic light emitting elements,
wherein the TFT layer comprises:
a plurality of electro-static discharge (ESD) protection circuits; and
a plurality of pixel circuits configured to drive the at least three inorganic light emitting elements for each pixel,

wherein each ESD protection circuit of the plurality of ESD protection circuits is surrounded by a plurality of adjacent pixels among the plurality of pixels,
wherein the plurality of adjacent pixels are arranged at a predetermined interval in a matrix array, and
wherein each inorganic light emitting element of the at least three inorganic light emitting elements is mounted on and electrically connected to a corresponding pixel circuit among the plurality of pixel circuits.

2. The display module as claimed in claim 1 , wherein each ESD protection circuit of the plurality of ESD protection circuits is located at a center of the plurality of adjacent pixels.

3. The display module as claimed in claim 1 , wherein the plurality of pixels are arranged in a plurality of pixel lines, the plurality of pixel lines comprising a plurality of outermost pixel lines, and
wherein the plurality of ESD protection circuits are disposed in the TFT layer such that none of the plurality of adjacent pixels is located in any outermost pixel line of the plurality of outermost pixel lines.

4. The display module as claimed in claim 1 , wherein the plurality of pixels of the display module are arranged in an entire area of the substrate at the predetermined interval.

5. The display module as claimed in claim 1 , wherein a first area of the TFT layer where each ESD protection circuit of the plurality of ESD protection circuits is disposed is different from a second area of the TFT layer where each pixel circuit of the plurality of pixel circuits is disposed.

6. The display module as claimed in claim 1 , wherein a number of the plurality of ESD protection circuits included in the display module is less than a number of the plurality of pixels of the display module.

7. The display module as claimed in claim 1 , wherein the plurality of pixels are arranged in a plurality of pixel lines, and
pixels of the plurality of pixels that are disposed in an outermost pixel line among the plurality of pixel lines are spaced from an edge of the substrate by a distance equal to or less than the predetermined interval.

8. The display module as claimed in claim 1 , wherein each ESD protection circuit among the plurality of ESD protection circuits is connected to at least one among a scan line, a data line, a power supply line, and a ground line for driving the plurality of pixel circuits.

9. The display module as claimed in claim 8 , wherein each ESD protection circuit of the plurality of ESD protection circuits comprises a first type ESD protection circuit comprising two TFTs configured to bypass static electricity flowing through the data line or the power supply line to the ground line.

10. The display module as claimed in claim 8 , wherein each ESD protection circuit of the plurality of ESD protection circuits comprises a second type ESD protection circuit comprising a transistor configured to cause the scan line, the data line, the power supply line, and the ground line to have equal voltages by a capacitive coupling effect.

11. The display module as claimed in claim 8 , wherein the scan line, the data line, and the ground line are connected to a first type ESD protection circuit comprising two TFTs configured to bypass static electricity flowing through the data line to the ground line, and
wherein the power supply line is connected to a second type ESD protection circuit comprising a transistor configured to cause the scan line, the data line, the power supply line, and the ground line to have equal voltages by a capacitive coupling effect.

12. A display panel comprising a plurality of display modules that are consecutively arranged, each display module of the plurality of display modules comprising:
a substrate;
a thin film transistor (TFT) layer formed on the substrate; and
a plurality of pixels disposed on the TFT layer;
wherein each pixel of the plurality of pixels comprises at least three inorganic light emitting elements,
wherein the TFT layer comprises:
a plurality of electro-static discharge (ESD) protection circuits, and
a plurality of pixel circuits configured to drive the at least three inorganic light emitting elements for each pixel,

wherein each ESD protection circuit of the plurality of ESD protection circuits is surrounded by a plurality of adjacent pixels among the plurality of pixels,
wherein the plurality of adjacent pixels are arranged at a predetermined interval in a matrix array, and
wherein each inorganic light emitting element of the at least three inorganic light emitting elements is mounted on and electrically connected to a corresponding pixel circuit among the plurality of pixel circuits.

13. The display panel as claimed in claim 12 , wherein a distance between pixels of the plurality of pixels that are arranged in a border region between a first display module and a second display module adjacent to the first display module among the plurality of display modules is equal to the predetermined interval.

14. The display panel as claimed in claim 12 , wherein each ESD protection circuit of the plurality of ESD protection circuits is located at a center of the plurality of adjacent pixels.

15. The display panel as claimed in claim 12 , wherein the plurality of pixels are arranged in a plurality of pixel lines, the plurality of pixel lines comprising a plurality of outermost pixel lines, and
wherein the plurality of ESD protection circuits are disposed in the TFT layer such that none of the plurality of adjacent pixels is located in any outermost pixel line of the plurality of outermost pixel lines.

16. The display panel as claimed in claim 12 , wherein the plurality of pixels are arranged in an entire area of the substrate at the predetermined interval.

17. The display panel as claimed in claim 12 , wherein a first area of the TFT layer where each ESD protection circuit of the plurality of ESD protection circuits is disposed is different from a second area of the TFT layer where each pixel circuit of the plurality of pixel circuits is disposed.

18. The display panel as claimed in claim 12 , wherein a number of the plurality of ESD protection circuits included in each display module of the plurality of display modules is less than a number of the plurality of pixels of each display module of the plurality of display modules.

19. The display panel as claimed in claim 12 , wherein the plurality of pixels are arranged in a plurality of pixel lines, and
pixels of the plurality of pixel lines that are disposed in an outermost pixel line among the plurality of pixel lines are spaced from an edge of the substrate by a distance equal to about ½ of the predetermined interval.

20. The display panel as claimed in claim 12 , wherein each ESD protection circuit among the plurality of ESD protection circuits is connected to at least one among a scan line, a data line, a power supply line, and a ground line for driving the plurality of pixel circuits.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jinho
• Shin Sangmin
• Lee Hoseop

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title