Shift register unit using clock signals, gate drive circuit, display panel, display device and driving method

Patent metadata

Field	Value
Publication number	US-11238805-B2
Application number	US-201916766450-A
Country	US
Kind code	B2
Filing date	Nov 4, 2019
Priority date	Jan 18, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-unit and a leakage prevention circuit; the first sub-unit includes a first input circuit and a first output circuit. The first input circuit controls a level of a first node in response to a first input signal, the first output circuit provides an output signal at an output terminal under control of the level of the first node, the leakage prevention circuit is connected to the first node and a first voltage terminal, and controls a level of a leakage prevention node under control of the level of the first node, whereby a conductive path is formed between the leakage prevention node and the first voltage terminal, and a circuit connected between the first node and the leakage prevention node is turned off.

First claim

What is claimed is:

1. A shift register unit, comprising a first sub-unit and a leakage prevention circuit, and the first sub-unit comprises a first input circuit, a first output circuit, a blanking input sub-unit and a second sub-unit, wherein
the first input circuit is configured to control a level of a first node in response to a first input signal,
the first output circuit is configured to provide an output signal at an output terminal under control of the level of the first node, and
the leakage prevention circuit is connected to the first node and a first voltage terminal, and is configured to control a level of a leakage prevention node under control of the level of the first node, so as to form a conductive path between the leakage prevention node and the first voltage terminal and turn off a circuit connected between the first node and the leakage prevention node,
wherein the leakage prevention circuit comprises a first leakage prevention sub-circuit and a second leakage prevention sub-circuit,
the first leakage prevention sub-circuit is connected to the first node and the leakage prevention node, and is configured to control the level of the leakage prevention node under control of the level of the first node, and
the second leakage prevention sub-circuit is connected to the leakage prevention node and the first voltage terminal, and the second leakage prevention sub-circuit is configured to form the conductive path between the leakage prevention node and the first voltage terminal under control of the level of the leakage prevention node or the level of the first node,

the blanking input sub-unit is connected to the first node, and is configured to receive a selection control signal and control the level of the first node;
the second sub-unit comprises a second input circuit and a second output circuit, the second input circuit is configured to control a level of a second node in response to the first input signal, and the second output circuit is configured to output a second output signal under control of the level of the second node, and wherein
the second output signal of the second output circuit and the first output signal of the first output circuit correspond to a same stage of the shift register unit, and the second output signal of the second output circuit is used for compensating a row of sub-pixel units during a blanking period of one frame.

2. The shift register unit according to claim 1 , wherein the first leakage prevention sub-circuit comprises a first leakage prevention transistor, and the second leakage prevention sub-circuit comprises a second leakage prevention transistor;
a gate electrode of the first leakage prevention transistor is connected to the first node, a first electrode of the first leakage prevention transistor is configured to receive a second voltage, and a second electrode of the first leakage prevention transistor is connected to the leakage prevention node; and
a gate electrode of the second leakage prevention transistor and a first electrode of the second leakage prevention transistor are configured to be connected to the leakage prevention node, and a second electrode of the second leakage prevention transistor is configured to be connected to the first voltage terminal.

3. The shift register unit according to claim 1 , wherein the first leakage prevention sub-circuit comprises a first leakage prevention transistor, and the second leakage prevention sub-circuit comprises a third leakage prevention transistor;
a gate electrode of the first leakage prevention transistor is connected to the first node, a first electrode of the first leakage prevention transistor is configured to receive a second voltage, and a second electrode of the first leakage prevention transistor is connected to the leakage prevention node; and
a gate electrode of the third leakage prevention transistor is connected to the first node, a first electrode of the third leakage prevention transistor is connected to the leakage prevention node, and a second electrode of the third leakage prevention transistor is configured to be connected to the first voltage terminal.

4. The shift register unit according to claim 1 , wherein the blanking input sub-unit comprises a selection control circuit, a third input circuit, and a first transmission circuit;
the selection control circuit is configured to control a level of a third node using a second input signal in response to the selection control signal, and maintain the level of the third node;
the third input circuit is configured to transmit a first clock signal to a fourth node under control of the level of the third node; and
the first transmission circuit is electrically connected to the first node, the fourth node, and the leakage prevention node, and is configured to control the level of the first node and the level of the leakage prevention node in respond to the first clock signal.

5. The shift register unit according to claim 4 , wherein
the blanking input sub-unit further comprises a second transmission circuit, and the second transmission circuit is electrically connected to the second node and the leakage prevention node, and is configured to transmit the level of the leakage prevention node to the second node in respond to the first clock signal.

6. The shift register unit according to claim 5 , wherein the first transmission circuit comprises a first transmission transistor and a second transmission transistor, and the second transmission circuit comprises a third transmission transistor;
a gate electrode of the first transmission transistor is configured to receive the first clock signal, a first electrode of the first transmission transistor is connected to the fourth node, and a second electrode of the first transmission transistor is connected to the leakage prevention node;
a gate electrode of the second transmission transistor is configured to receive the first clock signal, a first electrode of the second transmission transistor is connected to the leakage prevention node, and a second electrode of the second transmission transistor is connected to the first node; and
a gate electrode of the third transmission transistor is configured to receive the first clock signal, a first electrode of the third transmission transistor is connected to the leakage prevention node, and a second electrode of the third transmission transistor is connected to the second node.

7. The shift register unit according to claim 5 , wherein the first input circuit comprises a first input transistor and a second input transistor, and the second input circuit comprises a third input transistor;
a gate electrode of the first input transistor and a first electrode of the first input transistor are configured to receive the first input signal, and a second electrode of the first input transistor is connected to the leakage prevention node;
a gate electrode of the second input transistor is configured to receive the first input signal, a first electrode of the second input transistor is connected to the leakage prevention node, and a second electrode of the second input transistor is connected to the first node; and
a gate electrode of the third input transistor is configured to receive the first input signal, a first electrode of the third input transistor is connected to the leakage prevention node, and a second electrode of the third input transistor is connected to the second node.

8. The shift register unit according to claim 7 , wherein the second input circuit further comprises a fourth input transistor,
a gate electrode of the fourth input transistor and a first electrode of the fourth input transistor are configured to receive the first input signal, and a second electrode of the

Assignees

• Hefei Boe Joint Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Feng Xuehuan
• Li Yongqian
• Yuan Can
• Li Meng
• Ding Zehua
• Yuan Zhidong

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G3/3225

  using an active matrix · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title