Artificial reality system with verified boot sequences

Patent metadata

Field	Value
Publication number	US-11238159-B1
Application number	US-202016795254-A
Country	US
Kind code	B1
Filing date	Feb 19, 2020
Priority date	Nov 8, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

In general, techniques are described for improving security of a boot sequence of an application processor. In some examples, a computing device includes a first processor coupled to a first storage device, the first processor and first storage device configured to obtain firmware from a storage device external to the first processor; run a verification routine on the firmware; and in response to validation of the firmware with the verification routine, communicate the firmware to a second processor; and the second processor coupled to a second storage device, the second processor and second storage device configured to load the firmware.

First claim

What is claimed is:

1. A method comprising:
storing, within a memory of a boot processor, a firmware image retrieved from a storage device external to the boot processor, the firmware image including firmware required to boot another processor;
running, by the boot processor, a verification routine on the firmware image stored within the memory of the boot processor to validate the firmware in the firmware image;
executing a storage protocol at the boot processor to emulate, to the application processor, a storage device;
receiving at the boot processor, from an application processor, a request in the storage protocol for firmware needed to boot the application processor; and
transferring, using the storage protocol, the firmware requested to the application processor for use in booting the application processor.

2. The method of claim 1 ,
wherein the boot processor and the memory of the boot processor are components of a first System-on-Chip (SoC), and
wherein the storage device is external to the first SoC.

3. The method of claim 2 , wherein the application processor is a component of a second SoC.

4. The method of claim 1 , further comprising:
in response to validating the firmware with the verification routine, initiating, by the boot processor, a boot sequence of the application processor.

5. The method of claim 1 ,
wherein the storage protocol executed to emulate a storage device is different from a storage protocol used to retrieve the firmware image from the external storage device.

6. The method of claim 1 , wherein the boot processor boots using secure firmware stored to a secure storage device of a first System-on-Chip that includes the boot processor.

7. The method of claim 1 ,
storing, by the boot processor, the firmware to an embedded storage device of a first System-on-Chip that includes the boot processor,
wherein the embedded storage device comprises non-volatile memory.

8. The method of claim 1 , wherein transferring the firmware requested to the application processor comprises verifying traces between the first boot processor and the application processor have not been physically compromised before transferring the firmware requested to the application processor.

9. The method of claim 1 , the method further comprising:
generating, by the application processor, artificial reality content for display at a head-mounted display.

10. A computing device comprising:
a first processor coupled to a first storage device, the first processor and first storage device configured to:
store, within the first storage device, firmware retrieved from a storage device external to the first processor, the firmware image including firmware required to boot another processor;
run, within the first processor, a verification routine on the retrieved firmware to validate the firmware;
execute at the first processor a storage protocol to emulate, to a second processor, the external storage device;
receive, at the first processor, a request from the second processor for firmware needed to boot the second processor; and
transfer the firmware requested to the second processor using the storage protocol.

11. The computing device of claim 10 , wherein the second processor is configured to execute a boot sequence based on the transferred firmware.

12. The computing device of claim 10 , further comprising:
a first System-on-Chip (SoC), the first SoC comprising the first processor and the first storage device, the first storage device an embedded storage device;
a second SoC,
wherein the second processor is a component of a second SoC, and
wherein the external storage device is external to the first SoC.

13. The computing device of claim 10 , wherein the first processor and first storage device are configured to, in response to validating the firmware with the verification routine, initiate a boot sequence of the second processor.

14. The computing device of claim 10 ,
wherein the first processor and the first storage device are configured to retrieve the firmware from the external storage device using a second storage protocol,
the second storage protocol being different than the storage protocol executed to emulate the external storage device.

15. The computing device of claim 10 , further comprising:
a first System-on-Chip that includes the first processor,
wherein the first processor is a boot processor that boots using secure firmware stored to a secure storage device of the first System-on-Chip.

16. The computing device of claim 10 , further comprising:
a first System-on-Chip that includes the first processor and the first storage device, the first storage device an embedded storage device,
wherein the embedded storage device comprises non-volatile memory.

17. The computing device of claim 10 , wherein to transfer the firmware requested to the second processor, the first processor and first storage device are configured to:
transfer the firmware to the second processor via traces after verifying that the traces have not been physically compromised.

18. The computing device of claim 10 , wherein the second processor comprises an application processor configured to generate artificial reality content for display at a head-mounted display.

19. An artificial reality system comprising:
a first System-on-Chip (SoC) comprising a first processor and an embedded storage device;
a storage device external to the first SoC; and
a second SoC comprising a second processor,
wherein the first processor is configured to:
store, within the embedded storage device, firmware transferred from the storage device external to the first SoC, the firmware required to boot the second processor;
execute a storage protocol to emulate, to the second processor, a storage device; and
in response to validating the firmware with a verification routine, transfer the firmware required to boot the second processor from the embedded storage device to the second processor via the storage protocol and initiate a boot of the second processor,

wherein the second processor is configured to obtain the firmware from the embedded storage device of the first SoC and to execute the firmware as part of a boot sequence.

Assignees

• Facebook Tech Llc

Inventors

• Clark-Lindh Teman David
• Mossawir Benjamin Joseph
• Bormann David Stanley

Classifications

• H04L67/131

  Protocols for games, networked simulations or virtual reality · CPC title

• G06F21/575 Primary

  Secure boot · CPC title

• H04N13/344

  with head-mounted left-right displays · CPC title

• G06F21/572 Primary

  Secure firmware programming, e.g. of basic input output system [BIOS] · CPC title

• G06F15/7821

  Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory · CPC title