Chips including classical and quantum computing processors

Patent metadata

Field	Value
Publication number	US-11238000-B2
Application number	US-202016863623-A
Country	US
Kind code	B2
Filing date	Apr 30, 2020
Priority date	Mar 21, 2014
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

An apparatus includes a substrate, a classical computing processor formed on the substrate, a quantum computing processor formed on the substrate, and one or more coupling components between the classical computing processor and the quantum computing processor, the one or more coupling components being formed on the substrate and being configured to allow data exchange between the classical computing processor and the quantum computing processor.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate;
a classical computing processor formed on the substrate;
a quantum computing processor formed on the substrate; and
one or more interprocessor coupling components between the classical computing processor and the quantum computing processor, the one or more interprocessor coupling components being formed on the substrate and being configured to allow data exchange between the classical computing processor and the quantum computing processor,
wherein the quantum computing processor comprises a plurality of quantum unit cells, each quantum unit cell of the plurality of quantum unit cells comprising a plurality of qubits,
wherein the classical computing processor comprises a plurality of classical unit cells, each classical unit cell of the plurality of classical unit cells comprising a plurality of active components, each active component configured to generate a classical bit, and
wherein, for each classical unit cell of the plurality of classical unit cells, a first subset of the plurality of active components is coupled, by the one or more interprocessor coupling components, to a respective first subset of qubits within a corresponding quantum unit cell of the plurality of quantum unit cells.

2. The apparatus of claim 1 , wherein, for each classical unit cell of the plurality of classical unit cells, a second subset of the plurality of active components is coupled to the first subset of the plurality of active components of the classical unit cell.

3. The apparatus of claim 1 , wherein, for each quantum unit cell of the plurality of quantum unit cells, at least one first qubit within the quantum unit cell is coupled to at least one other first qubit within the quantum unit cell, and at least one second qubit within the quantum unit cell is coupled to at least one second qubit within another quantum unit cell.

4. The apparatus of claim 1 , wherein the quantum computing processor is configured
to receive output data from the classical computing processor, and
use the received output data as input data for a quantum computation to be carried out by the quantum computing processor.

5. The apparatus of claim 4 , wherein the quantum computing processor is configured to be programmed using the output data.

6. The apparatus of claim 1 , wherein the one or more interprocessor coupling components comprise an array of superconducting cavity quantum electrodynamics (QED) transmission lines.

7. The apparatus of claim 1 , wherein each quantum unit cell comprises at least one Josephson junction.

8. The apparatus of claim 1 , wherein the classical computing processor comprises a plurality of reciprocal quantum logic gates.

9. The apparatus of claim 1 , wherein the one or more interprocessor coupling components comprise an inductive coupler.

10. The apparatus of claim 1 , wherein the one or more interprocessor coupling components connect an output of the classical computing processor to an input of the quantum computing processor.

11. The apparatus of claim 1 , wherein each of the quantum computing processor and the classical computing processor comprises a superconducting quantum interference device (SQUID).

12. The apparatus of claim 1 , wherein each of the quantum computing processor and the classical computing processor comprises at least one Josephson junction and an inductor.

13. The apparatus of claim 1 , wherein the one or more interprocessor coupling components comprise a superconducting wire.

14. The apparatus of claim 1 , wherein each of the quantum computing processor and the classical computing processor comprises electronic components comprising a superconducting material.

15. The apparatus of claim 14 , wherein the electronic components of the quantum computing processor and the electronic components of the classical computing processor comprise the same superconducting material.

16. The apparatus of claim 1 , wherein the classical computing processor formed on the substrate and the quantum computing processor formed on the substrate are part of a single chip.

17. The apparatus of claim 1 , wherein the one or more interprocessor coupling components between the classical computing processor and the quantum computing processor comprise a post-processing element,
the post-processing element being configured to do either or both of
(i) receiving first data from the quantum computing processor, modifying the first data, and sending the modified first data to the classical computing processor, and
(ii) receiving second data from the classical computing processor, modifying the second data, and sending the modified second data to the quantum computing processor.

18. An apparatus comprising:
a substrate;
a classical computing processor formed on the substrate;
a quantum computing processor formed on the substrate;
one or more interprocessor coupling components between the classical computing processor and the quantum computing processor, the one or more interprocessor coupling components being formed on the substrate and being configured to allow data exchange between the classical computing processor and the quantum computing processor; and
a magnetic component configured to impose a transverse magnetic field on the substrate,
the magnetic component further being configured to impose a transverse magnetic field of time-varying strength while the quantum computing processor is performing a first operation, and to impose a transverse magnetic field of zero or negligible strength while the classical computing processor is performing a second operation.

19. The apparatus of claim 18 , wherein the zero or negligible strength is compatible with dominating thermal excitation in the classical computing processor.

20. The apparatus of claim 3 , wherein, for each quantum unit cell of the plurality of quantum unit cells, the at least one second qubit within the quantum unit cell coupled to the at least one second qubit within another quantum unit cell is coupled by a ferromagnetic coupling.

Assignees

• Google Llc

Inventors

• Mohseni Masoud
• Neven Hartmut

Classifications

• G06N10/60

  Quantum algorithms, e.g. based on quantum optimisation, quantum Fourier or Hadamard transforms · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• G06N10/20

  Models of quantum computing, e.g. quantum circuits or universal quantum computers · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title