Hierarchical power management unit for low power and low duty cycle devices

Patent metadata

Field	Value
Publication number	US-11237620-B2
Application number	US-202016866416-A
Country	US
Kind code	B2
Filing date	May 4, 2020
Priority date	Sep 28, 2017
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

An apparatus is provided which comprises: a first Power Management Unit (PMU); and a second PMU, wherein the first PMU is to manage transition of the apparatus from a low power state to a first active state, wherein the second PMU is to manage transition of the apparatus from the first active state to a second active state, and wherein the second PMU is to be powered down while the apparatus is to be in the low power state.

First claim

We claim:

1. An apparatus comprising:
a first Power Management Unit (PMU); and
a second PMU, wherein the second PMU is to decide to pause or abort one or more pending tasks, and to return control to the first PMU, to enable the first PMU to transition the apparatus to a low power state.

2. The apparatus of claim 1 , wherein while the apparatus is in a first active state, the first PMU is to issue a notice in response to a charge level of a battery being less than anon-critical threshold.

3. The apparatus of claim 1 , wherein the first PMU is to manage transition of the apparatus from the low power state to an active state.

4. The apparatus of claim 3 , wherein the active state is a first active state, wherein the second PMU is to manage transition of the apparatus from the first active state to a second active state.

5. The apparatus of claim 1 , wherein the second PMU is to be powered down while the apparatus is to be in the low power state.

6. The apparatus of claim 1 , wherein the first and second PMUs are in separate dies.

7. The apparatus of claim 1 , wherein the first PMU is a first die, wherein the second PMU is in a second die, wherein the first die is to consume relatively low power compared to the second die.

8. The apparatus of claim 7 , wherein power to the second die is to be shut off while the apparatus is to be in the low power state.

9. The apparatus of claim 7 , wherein the first die comprises circuitry to harvest power from an energy source to recharge a battery.

10. The apparatus of claim 1 , wherein the second PMU is to manage a dynamic voltage frequency scaling for a processor.

11. The apparatus of claim 1 , wherein the first PMU is to manage transition of the apparatus from the low power state to another low power state.

12. The apparatus of claim 1 , while the apparatus is in the active state and in response to a charge level of a battery being less than a critical threshold, the first PMU is to override the second PMU and to force the apparatus to transition to the low power state.

13. The apparatus of claim 1 , wherein the first PMU is to power a power rail to a voltage specified by the second PMU, wherein the power rail is to power the second PMU.

14. The apparatus of claim 1 , wherein the second PMU is to control levels of voltage supplied from a power rail to individual ones of a plurality of voltage domains within a subsystem comprising the second PMU.

15. A system comprising:
a battery;
a memory:
a processor coupled to the memory and the battery; and
an antenna communicatively coupled to the processor, wherein the processor comprises:
a first Power Management Unit (PMU); and
a second PMU, wherein the second PMU is to decide to pause or abort one or more pending tasks, and to return control to the first PMU, to enable the first PMU to transition the processor to a low power state.

16. The system of claim 15 , wherein while the processor is in a first active state, the first PMU is to issue a warning in response to a charge level of a battery being less than anon-critical threshold.

17. The system of claim 15 , wherein the first PMU is to manage transition of the processor from the low power state to an active state.

18. The system of claim 17 , wherein the active state is a first active state, wherein the second PMU is to manage transition of the processor from the first active state to a second active state, wherein the second PMU is to be powered down while the processor is to be in the low power state.

19. An apparatus comprising:
a first die comprising a first Power Management Unit (PMU);

and a second die comprising a second PMU,
wherein the first die is to consume relatively less power compared to the second die; and
wherein the second PMU is to decide to pause or abort one or more pending tasks, and to return control to the first PMU, to enable the first PMU to transition the apparatus to a low power state.

20. The apparatus of claim 19 , wherein power to the second die is to be shut off while the apparatus is to be in the low power state.

Assignees

• Intel Corp

Inventors

• Kurian Dileep J
• Deshmukh Pranjali S
• Kabisthalam Muthukumar Sriram
• Gupta Ankit
• Karnik Tanay
• Arditti Ilitzky David
• Bhandari Saurabh

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title