Pixel structure and manufacturing method thereof, array substrate and display device

Patent metadata

Field	Value
Publication number	US-11237440-B2
Application number	US-201715769640-A
Country	US
Kind code	B2
Filing date	Aug 7, 2017
Priority date	Jan 4, 2017
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A pixel structure and a manufacturing method thereof, an array substrate and a display device are provided. The pixel structure includes: a signal line; a common electrode line an extension direction of which is same as an extension direction of the signal line; a transistor including a semiconductor layer which includes a source region and a drain region; a first storage electrode which is insulated from the common electrode line and is connected with the drain region of the semiconductor layer; and a second storage electrode which is connected with the common electrode line and is insulated from the first storage electrode. In the pixel structure, portions, between the signal line and the common electrode line, of the first storage electrode and the second storage electrode includes overlap with each other to form a first storage capacitance.

First claim

What is claimed is:

1. A pixel structure, comprising:
a signal line;
a common electrode line, wherein an extension direction of the common electrode line and an extension direction of the signal line are same as each other;
a transistor which comprises a semiconductor layer, wherein the semiconductor layer comprises a source region and a drain region;
a first storage electrode which is insulated from the common electrode line and is connected with the drain region of the semiconductor layer; and
a second storage electrode which is connected with the common electrode line, protrudes from the common electrode line towards the signal line, and is insulated from a support substrate the first storage electrode,
wherein each of the first storage electrode and the second storage electrode comprises a portion between the signal line and the common electrode line, an entirety of an orthographic projection of the second storage electrode on the support substrate is all located between an orthographic projection of the signal line on the support substrate and an edge of an orthographic projection of the common electrode line on the support substrate close to the signal line, and the portion of the first storage electrode overlaps the portion of the second storage electrode, to form a first storage capacitance between the first storage electrode and the second storage electrode, and
wherein the signal line, the common electrode line, the transistor, the first storage electrode and the second storage electrode are on the support substrate, and
an entirety of an orthographic projection of the first storage capacitance on the support substrate is all located between the orthographic projection of the signal line on the support substrate and the edge of the orthographic projection of the common electrode line on the support substrate close to the signal line, the orthographic projection of the first storage capacitance on the support substrate does not include a portion provided outside a region between the orthographic projection of the signal line on the support substrate and the edge of the orthographic projection of the common electrode line on the support substrate close to the signal line;
the pixel structure further comprises:
a third storage electrode on the support substrate, wherein the third storage electrode is connected with the first storage electrode and is insulated from the second storage electrode, and the third storage electrode overlaps the second storage electrode to form a third storage capacitance, and
an entirety of orthographic projections of portions, which overlap each other, of the third storage electrode and the second storage electrode on the support substrate are at least between the orthographic projection of the signal line on the support substrate and the edge of the orthographic projection of the common electrode line on the support substrate close to the signal line.

2. The pixel structure according to claim 1 , wherein the signal line and the common electrode line are in a same layer.

3. The pixel structure according to claim 1 , wherein the first storage electrode further overlaps the common electrode line to form a second storage capacitance.

4. The pixel structure according to claim 1 , wherein the first storage electrode and the semiconductor layer are in a same layer.

5. The pixel structure according to claim 1 , wherein the second storage electrode and the common electrode line are in a same layer.

6. The pixel structure according to claim 1 , wherein the third storage electrode is connected with the first storage electrode by a via hole, and an orthographic projection of the via hole on the support substrate is between the orthographic projection of the common electrode line on the support substrate and the orthographic projection of the signal line on the support substrate.

7. The pixel structure according to claim 1 , further comprising a pixel electrode, wherein the third storage electrode is between the pixel electrode and the first storage electrode, and the third storage electrode is connected with the pixel electrode.

8. The pixel structure according to claim 1 , wherein the semiconductor layer comprises a first extension portion and a second extension portion which are connected with each other, an extension direction of the first extension portion intersects an extension direction of the second extension portion, the first extension portion comprises the source region, and the second extension portion extends along the common electrode line and is connected with the first storage electrode.

9. The pixel structure according to claim 8 , wherein the second extension portion and the common electrode line are insulated from each other and overlap with each other to form a fourth storage capacitance.

10. The pixel structure according to claim 8 , further comprising a data line which intersects the common electrode line and is connected with the source region, wherein the data line overlaps the first extension portion.

11. The pixel structure according to claim 8 , wherein the first extension portion comprises the source region, a first channel region, a connection region, a second channel region and the drain region which are connected successively.

12. The pixel structure according to claim 11 , wherein the signal line is a gate line, and the first channel region and the signal line overlap with each other.

13. The pixel structure according to claim 12 , wherein the signal line comprises a protrusion portion, and the protrusion portion and the second channel region overlap each other.

14. An array substrate, comprising the pixel structure according to claim 1 .

15. A display device, comprising the array substrate according to claim 14 .

16. A manufacturing method of a pixel structure, comprising:
forming a signal line and a common electrode line which are spaced apart from each other on a support substrate;
forming a transistor on the support substrate, wherein the transistor comprises a semiconductor layer, and the semiconductor layer comprises a source region and a drain region;
forming a first storage electrode on the support substrate, wherein the first storage electrode is insulated from the common electrode line and is connected with the drain region of the semiconductor layer; and
forming a second storage electrode on the support substrate, and the second storage electrode is connected with the common electrode line, protrudes from the common electrode line towards the signal line, and is insulated from the first storage electrode,
wherein an entirety of an orthographic projection of the second storage electrode on the support substrate is all located between an orthographic projection of the signal line on the support substrate and an edge of an orthographic projection of the common electrode line on the support substrate close to the signal line, an entirety of an orthographic projection of the portion of the first storage electrode on the support substrate and an entirely of an orthographic projection of the portion, which overlaps the portion of the first storage electrode, of the second storage electrode on the support substrate are between the orthographic projection of the signal line on the support substrate and the edge of the orthographic projection of the common electrode line on the support substrate close to the signal line, to form a first storage capacitance between the first storage electrode and the second storage electrode,
an entirety of an orthographic projection of the first storage capacitance on the support substrate is all located

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Tech Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Ding Duolong
• Liu Huafeng
• Zhao Shengwei
• Sun Chaochao
• Wang Chao
• Lv Jingping
• Yang Meng
• Yang Lei
• Hu Chongliang
• Xie Lin
• Shun Bule
• Sun Shimin

Classifications

• G02F1/136213 Primary

  Storage capacitors associated with the pixel electrode · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F2201/121

  common or background · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F2201/123

  pixel · CPC title