Amplifiers

US11233487B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-11233487-B1
Application numberUS-202017014283-A
CountryUS
Kind codeB1
Filing dateSep 8, 2020
Priority dateSep 8, 2020
Publication dateJan 25, 2022
Grant dateJan 25, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The application describes method and apparatus for amplification. An amplifier circuit ( 300 ) is described for driving a load ( 101 ) connected between first and second output nodes ( 103 p, 103 n ) based on an input signal (Sin). The amplifier circuit includes first and second signal paths for generating respective first and second driving signals (Soutp and Soutn) at the first and second output nodes, each of the first and second signal paths comprising a respective sigma-delta modulator ( 301 p, 301 n ). A correlation controller ( 302 ) is configured to control the first and second signal paths to provide correlation between at least some noise components of the first and second driving signals.

First claim

Opening claim text (preview).

The invention claimed is: 1. An amplifier circuit for, in use, driving a load connected between first and second output nodes with respective first and second driving signals based on an input signal, the amplifier circuit comprising: a first signal path for generating the first driving signal at the first output node, the first signal path comprising a first sigma-delta modulator; a second signal path for generating the second driving signal at the second output node, the second signal path comprising a second sigma-delta modulator; and a correlation controller for controlling the first and second signal paths to provide correlation between at least some noise components of the first and second driving signals. 2. The amplifier circuit of claim 1 wherein the correlation controller comprises a cross-coupler configured to: generate a first cross-coupling signal based on signal content of the first signal path; generate a second cross-coupling signal based on signal content of the second signal path; add the first cross-coupling signal to the second signal path; and add the second cross-coupling signal to the first signal path. 3. The amplifier circuit of claim 2 where each of the first and second sigma-delta modulators comprises a respective loop filter and a quantizer. 4. The amplifier circuit of claim 3 wherein the cross-coupler is configured to generate the first cross-coupling signal based on a first quantization error signal derived from the first signal path and to generate the second cross-coupling signal based on a second quantization error signal derived from the second signal path. 5. The amplifier circuit of claim 4 wherein the cross-coupler is configured to derive the first and second quantization error signals by determining a difference between an output of the loop filter and an output of the quantizer for the respective first and second sigma-delta modulators. 6. The amplifier circuit of claim 4 wherein the cross-coupler comprises first and second processing modules for applying a defined function to the first and second quantization error signals respectively to generate the respective first and second cross-coupling signals. 7. The amplifier circuit of claim 6 wherein each of the first and second processing modules comprises a filter for filtering the relevant quantization error signal and a gain element for applying a gain based on a predefined coupling coefficient. 8. The amplifier circuit of claim 3 wherein the cross-coupler is configured to: add the first cross-coupling signal to the second signal path between the loop filter and quantizer of the second sigma-delta modulator; and add the second cross-coupling signal to the first signal path between the loop filter and quantizer of the first sigma-delta modulator. 9. The amplifier circuit of claim 1 wherein the correlation controller is configured to apply a common dither signal to the first and second signal paths. 10. The amplifier circuit of claim 9 comprising a dither generator for generating the common dither signal. 11. The amplifier circuit of claim 9 , wherein each of the first and second sigma-delta modulators comprises a respective loop filter and a quantizer and the correlation controller is configured to add the common dither signal to the respective first and second signal path between the loop filter and quantizer of the first and second sigma-delta modulators respectively. 12. The amplifier circuit of claim 1 wherein the first and second signal paths are coupled to an input node for receiving the input signal and the second signal path comprises an inverter upstream of the second sigma-delta modulator. 13. The amplifier circuit of claim 1 wherein the first and second signal paths comprise respective first and second output drivers between the respective first and second sigma-delta modulator and the respective first and second output node. 14. The amplifier circuit of claim 13 wherein the first and second output drivers comprise class-D output stages. 15. The amplifier circuit of claim 1 implemented as an integrated circuit. 16. The amplifier circuit of claim 1 further comprising an output transducer connected between the first and second output nodes. 17. The amplifier circuit of claim 16 wherein the output transducer comprises a piezoelectric output transducer. 18. An electronic device comprising the amplifier circuit of claim 1 . 19. An amplifier circuit for, in use, driving a load connected between first and second output nodes with respective first and second driving signals based on an input signal, the amplifier circuit comprising: a first signal path for generating the first driving signal, the first signal path comprising a first sigma-delta modulator with a first loop filter and a first quantizer; a second signal path for generating the second driving signal at the second output node, the second signal path comprising a second sigma-delta modulator with a second loop filter and a second quantizer; and a cross-coupler configured to: add a first coupling signal derived from the first sigma-delta modulator to an input of the second quantizer; and add a second coupling signal derived from the second sigma-delta modulator to an input of the first quantizer. 20. An amplifier circuit for, in use, driving a load connected between first and second output nodes with respective first and second driving signals based on an input signal, the amplifier circuit comprising: a first signal path for generating the first driving signal, the first signal path comprising a first sigma-delta modulator; a second signal path for generating the second driving signal at the second output node, the second signal path comprising a second sigma-delta modulator; and a correlation controller configured to apply a common dither signal to the first and second sigma-delta modulators.

Assignees

Inventors

Classifications

  • for correcting frequency response · CPC title

  • the amplifier being designed for audio applications · CPC title

  • Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

  • using dither · CPC title

  • using analogue-digital or digital-analogue conversion (H03F3/2173 takes precedence) · CPC title

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Frequently asked questions

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What does patent US11233487B1 cover?
The application describes method and apparatus for amplification. An amplifier circuit ( 300 ) is described for driving a load ( 101 ) connected between first and second output nodes ( 103 p, 103 n ) based on an input signal (Sin). The amplifier circuit includes first and second signal paths for generating respective first and second driving signals (Soutp and Soutn) at the first and sec…
Who is the assignee on this patent?
Cirrus Logic Int Semiconductor Ltd, Cirrus Logic Inc
What technology area does this patent fall under?
Primary CPC classification H03F3/2173. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 25 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).