Power amplifier linearization circuit and related apparatus

Patent metadata

Field	Value
Publication number	US-11233485-B2
Application number	US-202016816430-A
Country	US
Kind code	B2
Filing date	Mar 12, 2020
Priority date	Mar 12, 2020
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

A power amplifier linearization circuit and related apparatus is provided. In examples disclosed herein, the power amplifier linearization circuit includes an analog pre-distortion (APD) circuit coupled to an input of a power amplifier. Notably, the power amplifier can exhibit linearity response deviation, namely linearity amplitude response deviation and linearity phase response deviation, when amplifying a radio frequency (RF) signal under a compression condition. As such, the APD circuit is configured to receive a control signal corresponding to the linearity response deviation and pre-process the RF signal based on the control signal before providing the RF signal to the power amplifier. As a result, it may be possible to reduce the linearity response deviation in the power amplifier, thus helping to improve linearity and RF performance of the power amplifier.

First claim

What is claimed is:

1. A power amplifier linearization circuit comprising:
a signal input that receives a radio frequency (RF) signal;
a signal output that outputs the RF signal to a power amplifier configured to amplify the RF signal to generate an amplified RF signal; and
an analog pre-distortion (APD) circuit coupled between the signal input and the signal output, the APD circuit configured to:
receive a control signal corresponding to a linearity response deviation that comprises an amplitude response deviation and a phase response deviation of the power amplifier; and
process the RF signal based on the control signal to reduce the linearity response deviation.

2. The power amplifier linearization circuit of claim 1 wherein
the APD circuit is further configured to process the RF signal to reduce the amplitude response deviation and the phase response deviation.

3. The power amplifier linearization circuit of claim 1 wherein:
the amplitude response deviation comprises a positive amplitude response deviation and the phase response deviation comprises a positive phase response deviation; and
the APD circuit is further configured to process the RF signal to reduce the positive amplitude response deviation and the positive phase response deviation.

4. The power amplifier linearization circuit of claim 1 further comprising:
a control circuit coupled to the APD circuit and configured to generate the control signal comprising a control voltage in response to receiving a trigger voltage; and
a detection circuit coupled between the control circuit and the power amplifier and configured to:
detect the linearity response deviation of the power amplifier; and
generate the trigger voltage in response to detecting the linearity response deviation.

5. The power amplifier linearization circuit of claim 4 wherein the detection circuit comprises a transistor-based diode coupled between the control circuit and the power amplifier, the transistor-based diode configured to become conductive in response to the linearity response deviation to generate the trigger voltage.

6. The power amplifier linearization circuit of claim 5 wherein the detection circuit further comprises a resistor-capacitor (RC) circuit coupled between the control circuit and the transistor-based diode, the RC circuit configured to output the trigger voltage within a defined triggering bandwidth.

7. The power amplifier linearization circuit of claim 5 wherein the detection circuit is further configured to adjust the trigger voltage prior to providing the trigger voltage to the control circuit.

8. The power amplifier linearization circuit of claim 4 wherein the control circuit comprises:
a transistor network coupled to the detection circuit and configured to output an initial control voltage in response to receiving the trigger voltage; and
a voltage divider coupled between the transistor network and the APD circuit, the voltage divider configured to divide the initial control voltage to generate the control voltage.

9. The power amplifier linearization circuit of claim 4 wherein the APD circuit comprises:
a transistor coupled between the signal input and the signal output, the transistor comprising a base electrode coupled to the control circuit to receive the control voltage; and
a capacitor coupled in parallel to the transistor between the signal input and the signal output.

10. A power amplifier apparatus comprising:
a power amplifier configured to amplify a radio frequency (RF) signal to generate an amplified RF signal; and
a power amplifier linearization circuit comprising:
a signal input that receives the RF signal;
a signal output that outputs the RF signal to the power amplifier; and
an analog pre-distortion (APD) circuit coupled between the signal input and the signal output, the APD circuit configured to:
receive a control signal corresponding to a linearity response deviation that comprises an amplitude response deviation and a phase response deviation of the power amplifier; and
process the RF signal based on the control signal to reduce the linearity response deviation.

11. The power amplifier apparatus of claim 10 wherein
the APD circuit is further configured to process the RF signal to reduce the amplitude response deviation and the phase response deviation.

12. The power amplifier apparatus of claim 10 wherein:
the amplitude response deviation comprises a positive amplitude response deviation and the phase response deviation comprises a positive phase response deviation; and
the APD circuit is further configured to process the RF signal to reduce the positive amplitude response deviation and the positive phase response deviation.

13. The power amplifier apparatus of claim 10 wherein the power amplifier linearization circuit further comprises:
a control circuit coupled to the APD circuit and configured to generate the control signal comprising a control voltage in response to receiving a trigger voltage; and
a detection circuit coupled between the control circuit and the power amplifier and configured to:
detect the linearity response deviation of the power amplifier; and
generate the trigger voltage in response to detecting the linearity response deviation.

14. The power amplifier apparatus of claim 13 wherein the detection circuit is coupled between the control circuit and an output stage of the power amplifier.

15. The power amplifier apparatus of claim 14 wherein the detection circuit comprises a transistor-based diode coupled between the control circuit and the output stage of the power amplifier, the transistor-based diode configured to become conductive in response to the linearity response deviation to generate the trigger voltage.

16. The power amplifier apparatus of claim 15 wherein the detection circuit further comprises a resistor-capacitor (RC) circuit coupled between the control circuit and the transistor-based diode, the RC circuit configured to output the trigger voltage within a defined triggering bandwidth.

17. The power amplifier apparatus of claim 13 wherein the detection circuit is further configured to adjust the trigger voltage prior to providing the trigger voltage to the control circuit.

18. The power amplifier apparatus of claim 13 wherein the control circuit comprises:
a transistor network coupled to the detection circuit and configured to output an initial control voltage in response to receiving the trigger voltage; and
a voltage divider coupled between the transistor network and the APD circuit, the voltage divider configured to divide the initial control voltage to generate the control voltage.

19. The power amplifier apparatus of claim 18 wherein the transistor network comprises at least two transistors coupled in parallel between the detection circuit and the voltage divider.

20. The power amplifier apparatus of claim 13 wherein the APD circuit comprises:
a transistor coupled between the signal input and the signal output, the transistor comprising a base electrode coupled to the control circuit to receive the control voltage; and
a capacitor coupled in parallel to the transistor between the signal input and the signal output.

Assignees

• Qorvo Us Inc

Inventors

• Zybura Michael F
• Moriuchi Toshiaki
• Scott Baker
• Cho Mikyung
• Spears Edward T

Classifications

• H03F1/3241 Primary

  using predistortion circuits (H03F1/3211, H03F1/3217 take precedence) · CPC title

• H03F2201/3231

  Adaptive predistortion using phase feedback from the output of the main amplifier · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F3/21

  with semiconductor devices only {(H03F3/245 takes precedence)} · CPC title