Signal generator

Patent metadata

Field	Value
Publication number	US-11233480-B2
Application number	US-202017128882-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Dec 20, 2019
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

A signal generator has a nominal frequency control input and a modulation frequency control input and comprises an oscillator, with a first set of capacitors at least partially switchably connectable for adjusting a frequency of the oscillator as part of a phase-locked loop, and a second set of capacitors comprised in a modulation stage of the oscillator, switchably connectable for modulating the frequency and controlled by the modulation frequency control input; a modulation gain estimation stage configured to determine a frequency-to-capacitor modulation gain; and a modulation range reduction module configured for clipping a modulation range of the oscillator to a range achievable using the second set of capacitors, using the modulation gain averaging out, in time, a phase error caused by the said clipping; and mimicking the said clipping, additively output to the nominal frequency control input to compensate said PLL for the said modulation.

First claim

What is claimed is:

1. A signal generator having:
a nominal frequency control input, and
a modulation frequency control input and comprising:
an oscillator, with:
a first set of capacitors at least partially switchably connectable for adjusting a frequency of said oscillator as part of a phase-locked loop, PLL, as set by the nominal frequency control input, and
a second set of capacitors comprised in a modulation, MOD, stage of the oscillator, switchably connectable for modulating the frequency and controlled by the modulation frequency control input;
a modulation gain estimation stage configured to determine, derived from the modulation frequency control input and a state of the PLL, a frequency-to-capacitor modulation gain; and
a modulation range reduction module connected between the modulation frequency input and the modulation stage and configured for:
clipping a modulation range of the oscillator to a range achievable using the second set of capacitors, using the modulation gain;
averaging out, in time, a phase error caused by the clipping; and
mimicking the clipping, additively output to the nominal frequency control input to compensate the PLL for the modulation.

2. The signal generator of claim 1 , wherein the state of the PLL is a time-to-digital converter, TDC, output.

3. The signal generator of claim 1 , wherein the modulation range reduction module comprises a modulation range reduction block providing the clipping and the averaging, the modulation range reduction block comprising:
an input block converting the modulation frequency control to units of capacitors using the modulation gain;
a quantization and limiting block providing the clipping and output to the modulation stage; and
a delay block input with a difference between an input and an output of the quantization and limiting block and additively output to the input of the quantization and limiting block.

4. The signal generator of claim 1 , wherein the modulation range reduction module comprises a compensation branch block providing the mimicking, the compensation branch block comprising:
a quantization and limiting block mimicking the clipping of the of the modulation range reduction block; and
a delay block input with a difference between an input and an output of the quantization and limiting block and additively output to the input of the quantization and limiting block.

5. The signal generator of claim 1 , wherein the oscillator is a digitally-controlled oscillator, DCO.

6. The signal generator of claim 5 , wherein the capacitances of the first set of capacitors and the second set of capacitors are added together for digitally controlling the frequency of the DCO.

7. The signal generator of claim 6 , wherein first set of capacitors and the second set of capacitors comprise a process voltage and temperature, PTV, bank for coarse frequency control.

8. The signal generator of claim 7 , wherein the PTV bank comprises a fixed capacitance.

9. The signal generator of claim 6 , wherein the first set of capacitors and the second set of capacitors comprise an ACQ bank for medium frequency control.

10. The signal generator of claim 9 , wherein the ACQ bank comprises a fixed capacitance.

11. The signal generator of claim 6 , wherein the first set of capacitors and the second set of capacitors comprise a TRK bank for fine frequency control.

12. The signal generator of claim 11 , wherein the TRK bank comprises a fixed capacitance.

13. The signal generator of claim 1 , wherein the PLL is an all-digital phase-locked loop, AD-PLL.

14. The signal generator of claim 1 , wherein the signal generator forms part of a wireless transmitter.

15. The signal generator of claim 1 , wherein the signal generator forms part of a wireless transceiver.

Assignees

• Stichting Imec Nederland

Inventors

• Van Den Heuvel Johan

Classifications

• H03C3/0958

  applying frequency modulation by varying the characteristics of the voltage controlled oscillator · CPC title

• H03C3/0941

  applying frequency modulation at more than one point in the loop · CPC title

• H03C3/0991 Primary

  including calibration means or calibration methods · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title