Array substrate with static charge releasing pattern and method for producing the same

Patent metadata

Field	Value
Publication number	US-11233016-B2
Application number	US-201916601351-A
Country	US
Kind code	B2
Filing date	Oct 14, 2019
Priority date	Jan 4, 2016
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

An array substrate and a method for producing the same are disclosed. The array substrate includes a metal pattern and an electrically conductive pattern sequentially formed on a base substrate, the electrically conductive pattern being insulated from the metal pattern. The array substrate further includes a static charge releasing pattern formed in a same layer and made of a same material as the electrically conductive pattern, and which is insulated from the electrically conductive pattern. The metal pattern is a signal line running through a display area of the array substrate, and includes an input end, an output end, and a body portion between the input end and the output end. The output end of the signal line includes an island-like structure, and a width of the island-like structure is greater than that of the body portion. The static charge releasing pattern is electrically connected with the island-like structure.

First claim

What is claimed is:

1. An array substrate, comprising a metal pattern and an electrically conductive pattern which are sequentially formed on a base substrate, the electrically conductive pattern being insulated from the metal pattern, wherein the array substrate further comprises:
a static charge releasing pattern formed in a same layer as the electrically conductive pattern and made of a same material as the electrically conductive pattern, the static charge releasing pattern being insulated from the electrically conductive pattern and electrically connected with the metal pattern,
wherein the metal pattern is a signal line which runs through a display area of the array substrate, and the signal line comprises:
an input end;
an output end; and
a body portion between the input end and the output end,

wherein the output end of the signal line comprises an island-like structure, and a width of the island-like structure is greater than a width of the body portion, and
wherein the static charge releasing pattern is electrically connected with the island-like structure.

2. The array substrate according to claim 1 , wherein an insulating layer is disposed between the electrically conductive pattern and the metal pattern, a via hole is disposed in the insulating layer, and the static charge releasing pattern is electrically connected to the metal pattern through the via hole.

3. The array substrate according to claim 1 , wherein the metal pattern is a gate line, the array substrate comprises a plurality of rows of pixels and a plurality of gate lines, each of the plurality of gate lines is connected to a row of pixels, an input end of an odd gate line connected with an odd row of pixels is connected to a first gate line driving circuit, and an input end of an even gate line connected with an even row of pixels is connected to a second gate line driving circuit, wherein an output end of the odd gate line connected with the odd row of pixels is located on a side of the display area, and an output end of the even gate line connected with the even row of pixels is located on the other side of the display area opposite to the side.

4. The array substrate according to claim 1 , wherein the island-like structure is rectangular.

5. The array substrate according to claim 1 , wherein the first static charge releasing pattern is in a shape of a rectangle having an area of 25 μm 2 to 400 μm 2 .

6. The array substrate according to claim 1 , wherein an orthographic projection of the static charge releasing pattern on the base substrate at least partially overlaps an orthographic projection of the island-like structure on the base substrate.

7. The array substrate according to claim 2 , wherein the static charge releasing pattern is electrically connected with the island-like structure through at least two via holes in the insulating layer.

8. The array substrate according to claim 1 , further comprising:
a common electrode signal line disposed in the same layer as the metal pattern and adjacent to the display area,
wherein the common electrode signal line has a groove whose opening is disposed toward the display area, and the island-like structure is disposed in the groove.

9. The array substrate according to claim 1 , wherein the metal pattern is a gate line, and the electrically conductive pattern comprises a source-drain metal layer pattern.

10. The array substrate according to claim 9 , wherein the electrically conductive pattern further comprises a data line.

11. The array substrate according to claim 1 , wherein the metal pattern is a gate line, and the electrically conductive pattern comprises a transparent electrode.

12. The array substrate according to claim 11 , wherein the transparent electrode comprises a pixel electrode or a common electrode.

13. The array substrate according to claim 1 , wherein the metal pattern is a data line, and the electrically conductive pattern comprises a transparent electrode.

14. The array substrate according to claim 13 , wherein the transparent electrode comprises a pixel electrode or a common electrode.

15. A method for producing an array substrate, comprising a step of sequentially forming a metal pattern and an electrically conductive pattern on a base substrate, the electrically conductive pattern being insulated from the metal pattern;
wherein in a patterning process for forming the electrically conductive pattern, a static charge releasing pattern insulated from the electrically conductive pattern and electrically connected with the metal pattern is also formed, the static charge releasing pattern being formed in a same layer as the electrically conductive pattern and made of a same material as the electrically conductive pattern, and
wherein the metal pattern is a signal line which runs through a display area of the array substrate, and the signal line comprises:
an input end;
an output end; and
a body portion between the input end and the output end,
wherein the output end of the signal line comprises an island-like structure, and a width of the island-like structure is greater than a width of the body portion, and
wherein the static charge releasing pattern is electrically connected with the island-like structure.

16. The method according to claim 15 , further comprising:
a step of forming an insulating layer which is disposed between the electrically conductive pattern and the metal pattern and has a via hole;
wherein the static charge releasing pattern is electrically connected to the island-like structure through the via hole.

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Yang Xiaofei
• Mo Zailong
• Xin Yanxia
• Dai Ke
• Zhu Yawen
• Su Lei

Classifications

• H10W42/60 Primary

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/431

  having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title