Method of manufacturing display apparatus

Patent metadata

Field	Value
Publication number	US-11227880-B2
Application number	US-202016832613-A
Country	US
Kind code	B2
Filing date	Mar 27, 2020
Priority date	Aug 21, 2019
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

A method of manufacturing a display apparatus includes forming a first conductive layer on a base substrate including a panel area and a margin area disposed next to the panel area, the margin area including a dummy pattern area, forming a photoresist layer on the first conductive layer, forming a photoresist pattern by exposing and developing the photoresist layer, forming a first conductive pattern by etching the first conductive layer using the photoresist pattern, and removing the photoresist pattern. The forming the first conductive pattern includes forming a first pixel circuit pattern in the panel area, and forming a dummy pattern in the dummy pattern area of the margin area. An opening ratio of a portion where the dummy pattern is not formed with respect to the dummy pattern area is about 30% or more.

First claim

What is claimed is:

1. A method of manufacturing a display apparatus, comprising:
forming a first conductive layer on a base substrate including a panel area and a margin area disposed next to the panel area, the margin area including a dummy pattern area;
forming a photoresist layer on the first conductive layer;
forming a photoresist pattern by exposing and developing the photoresist layer;
forming a first conductive pattern by etching the first conductive layer using the photoresist pattern, the forming the first conductive pattern including:
forming a first pixel circuit pattern in the panel area; and
forming a dummy pattern in the dummy pattern area of the margin area; and

removing the photoresist pattern,
wherein an opening ratio of a portion where the dummy pattern is not formed with respect to the dummy pattern area is about 30% or more.

2. The method of claim 1 , wherein the opening ratio of the dummy pattern area is about 60% or less.

3. The method of claim 1 , wherein the dummy pattern has a repeating pattern and is uniformly formed with respect to the dummy pattern area.

4. The method of claim 1 , wherein the dummy pattern has a shape in which a plurality of rectangles are arranged along a first direction and a second direction perpendicular to the first direction.

5. The method of claim 4 , wherein a distance between neighboring rectangles of the dummy pattern is more than about 20 μm (micrometer).

6. The method of claim 1 , wherein the margin area includes a dummy active area, the method further comprising:
forming an active layer including an active pattern of a thin film transistor in the panel area and a dummy active pattern in the dummy active area.

7. The method of claim 6 , wherein the dummy active area is between the panel area and the dummy pattern area.

8. The method of claim 1 , wherein
the margin area includes an edge area at an edge of the base substrate,
the dummy pattern area is between the edge area and the panel area, and
the first conductive pattern is not formed in the edge area.

9. The method of claim 1 , wherein the forming the first conductive pattern includes wet etching the first conductive layer using an organic acid etchant.

10. The method of claim 1 , wherein the forming the first pixel circuit pattern of the first conductive pattern includes forming a gate electrode or source and drain electrodes of a thin film transistor.

11. The method of claim 10 , wherein the first conductive layer includes at least one of gold, silver, aluminum, platinum, nickel, titanium, palladium, magnesium, calcium, lithium, chromium, tantalum, molybdenum, scandium, neodymium, iridium, alloy containing aluminum, aluminum nitride, alloys containing silver, tungsten, tungsten nitride, alloys containing copper, alloys containing molybdenum, titanium nitride, tantalum nitride, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, and indium zinc oxide.

12. The method of claim 1 , wherein the forming the first pixel circuit pattern of the first conductive pattern includes forming a pixel electrode electrically connected to a thin film transistor.

13. The method of claim 12 , wherein the forming the first conductive layer includes forming a layer containing silver (Ag).

14. The method of claim 13 , wherein the forming the first conductive layer comprises:
forming a layer comprising at least one indium tin oxide; and
forming a layer comprising at least one silver (Ag).

15. The method of claim 12 , further comprising:
forming a light emitting layer and an opposite electrode on the pixel electrode.

16. The method of claim 1 , further comprising:
forming an insulating layer on the first conductive pattern; and
forming a second conductive pattern on the insulating layer.

17. The method of claim 16 , wherein the forming the second conductive pattern includes:
forming a second pixel circuit pattern in the panel area; and
forming a second dummy pattern in the dummy pattern area of the margin area.

18. The method of claim 1 , further comprising:
cutting the margin area of the base substrate to separate the margin area from the panel area.

Assignees

• Samsung Display Co Ltd

Inventors

• Park Jonghee
• Kim Jin Seock

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/71 Primary

  using masks for conductive or resistive materials · CPC title

• H10K59/88

  Dummy elements, i.e. elements having non-functional features · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title