Optimized pixel shader attribute management

Patent metadata

Field	Value
Publication number	US-11227430-B2
Application number	US-201916597840-A
Country	US
Kind code	B2
Filing date	Oct 9, 2019
Priority date	Jun 19, 2019
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

According to one general aspect, an apparatus may include a graphical processing engine comprising a pipeline having a plurality of substantially sequential circuit stages, the pipeline comprising a front-end output logic circuit configured to substantially separate position information into a position information pipeline portion, and non-position information in a non-position information pipeline portion. Wherein the pipeline is configured to perform a multi-stage culling of data.

First claim

What is claimed is:

1. An apparatus comprising:
a graphical processing engine comprising a pipeline having a plurality of substantially sequential circuit stages, the pipeline comprising:
a front-end output logic circuit configured to receive attribute data of graphical data, the attribute data comprising position data and non-position data, the front-end output logic circuit further configured to output the position data into a position data path of the pipeline and output the non-position data into a non-position data path of the pipeline,
wherein the position data path of the pipeline is configured to:
perform a multi-stage culling of positional data, and
cause non-positional data corresponding to culled positional data to be removed from the non-position data path of the pipeline based on feeding back culling information to the front-end output logic circuit for removal of non-positional data.

2. The apparatus of claim 1 , wherein the front-end output logic circuit is configured to:
cull non-positional data corresponding to culled positional data, preventing the non-positional data corresponding to the culled positional data from being received by a subsequent pipeline circuit stage.

3. The apparatus of claim 1 , wherein the pipeline comprises a culling circuit configured to:
cull primitive data based, at least in part, upon primitive characteristics; and
prevent non-positional data corresponding to culled primitive data from being processed by a subsequent pipeline circuit stage.

4. The apparatus of claim 1 , wherein the pipeline comprises a rasterization circuit configured to:
cull primitive data based, at least in part, upon visibility determination; and
prevent non-positional data corresponding to culled visibility data from being processed by a subsequent pipeline circuit stage.

5. The apparatus of claim 1 , wherein the pipeline comprises a culling circuit and a rasterization circuit, wherein the front-end output logic circuit, the culling circuit, and the front-end output logic circuit are placed substantially in series, and each performs a culling operation to reduce an amount of data passed to a next pipeline stage, wherein at least the front-end output logic circuit, the culling circuit, and the front-end output logic circuit form a multi-stage culling portion of the pipeline.

6. The apparatus of claim 1 , wherein the pipeline comprises an attribute setup circuit and a culling circuit; and
wherein the non-position data is routed from the front-end output logic circuit to the attribute setup circuit, and
wherein the position data is routed from the front-end output logic circuit to the culling circuit.

7. The apparatus of claim 6 , wherein the attribute setup circuit is configured to delay primitive attribute interpolation setup until after primitive data has been culled.

8. The apparatus of claim 1 , wherein the pipeline is configured to perform the multi-stage culling of data by culling attribute data before culling primitive data.

9. The apparatus of claim 1 , wherein the pipeline comprises a culling circuit and at least one subsequent processing circuit stage, architecturally after the culling circuit;
wherein the front-end output logic circuit is configured to:
receive an indication from the culling circuit regarding which data to cull,
read surviving data from a front-end output buffer, and
as needed, pass surviving data, or a portion thereof, to the at least one subsequent processing circuit stage for processing.

10. A system comprising:
a processor core configured to process instructions; and
a graphics core configured to render graphical data, wherein the graphics core comprises a graphics processing pipeline comprising a plurality of circuit stages substantially sequentially arranged to at least partially process the graphical data as the graphical data flows through the graphics processing pipeline, the graphical data comprising positional data and non-positional data,
wherein the circuit stages include:
a front-end output logic circuit configured to receive the graphical data and to provide un-culled graphical data to one or more subsequent circuit stages, and remove culled graphical data from the graphics processing pipeline; and
a multi-stage culling portion of a positional information portion of the circuit stages that is subsequent to the front-end output logic and is configured to feedback to the front-end output logic circuit which non-positional data to cull from the graphical data received by the front-end output logic circuit.

11. The system of claim 10 , wherein the front-end output logic circuit is configured to:
determine unneeded positional data that is not needed by a subsequent pipeline circuit stage; and
cull graphical data corresponding to the unneeded positional data, preventing the graphical data corresponding to the unneeded positional data from being processed by the subsequent pipeline circuit stage.

12. The system of claim 10 , wherein the pipeline comprises a culling circuit configured to:
cull primitive data based, at least in part, upon primitive characteristics; and
prevent graphical data corresponding to the culled primitive data from being processed by a subsequent pipeline circuit stage.

13. The system of claim 10 , wherein the pipeline comprises a rasterization circuit configured to:
cull primitive data based, at least in part, upon visibility determination; and
prevent graphical data corresponding to the culled primitive data from being processed by a subsequent pipeline circuit stage.

14. The system of claim 10 , wherein the multi-stage culling portion comprises a culling circuit and a rasterization circuit, and
wherein the front-end output logic circuit, the culling circuit, and the front-end output logic circuit are placed substantially in series, and each circuit performs a culling operation to reduce an amount of data passed to a next pipeline stage.

15. The system of claim 10 , wherein the pipeline comprises an attribute setup circuit and a culling circuit; and
wherein non-position information is routed from the front-end output logic circuit to the attribute setup circuit, and
wherein position information is routed from the front-end output logic circuit to the culling circuit.

16. The system of claim 15 , wherein the attribute setup circuit is configured to delay primitive attribute interpolation setup until after primitive data has been culled.

17. The system of claim 10 , wherein the pipeline is configured to perform a multi-stage culling of data by culling attribute data before culling primitive data.

18. The system of claim 10 , wherein the pipeline comprises a culling circuit and at least one subsequent processing circuit stage, architecturally after the culling circuit;
wherein the front-end output logic circuit is configured to:
receive an indication from the culling circuit regarding which graphical data to cull,
read un-culled graphical data from a front-end output buffer, and
as needed, pass the un-culled graphical data, or a portion thereof, to the at least one subsequent processing circuit stage for processing.

19. A method, comprising:
receiving, at a front-end output logic circuit of a graphical pipeline, graphical data from one or more front-end output buffers, the graphical data comprising positional data and non-positional data;
determining at a culling circuit that is subsequent to the front-end output logic circuit in the graphical pipeline which graphical data may be removed based on positional d

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lentz Derek
• Goodman Chris

Classifications

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T1/60

  Memory management · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/40 Primary

  Hidden part removal · CPC title

• G06T15/80

  Shading · CPC title