Scalable matrix node engine with configurable data formats

Patent metadata

Field	Value
Publication number	US-11227029-B2
Application number	US-201916421225-A
Country	US
Kind code	B2
Filing date	May 23, 2019
Priority date	May 3, 2019
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

A microprocessor system comprises a matrix computational unit and a control unit. The matrix computational unit includes one or more processing elements. The control unit is configured to provide a matrix processor instruction to the matrix computational unit. The matrix processor instruction specifies a floating-point operand formatted with an exponent that has been biased with a specified bias.

First claim

What is claimed is:

1. A microprocessor system, comprising:
a matrix computational unit that includes one or more processing elements; and
a control unit configured to provide a matrix processor instruction to the matrix computational unit, wherein the matrix processor instruction specifies a floating-point operand formatted with an exponent that has been biased with a specified bias, wherein the floating-point operand is a matrix,
wherein the specified bias is configurable via the control unit using the matrix processor instruction, and wherein the matrix processor instruction specifies a floating-point number format for the floating-point operand from a group of floating-point formats.

2. The system of claim 1 , wherein each element of the matrix uses an 8-bit floating-point format.

3. The system of claim 2 , wherein the 8-bit floating-point format allocates 1-bit for a sign bit, 4-bits for an exponent field, and 3-bits for a mantissa field.

4. The system of claim 2 , wherein the 8-bit floating-point format allocates 1-bit for a sign bit, 5-bits for an exponent field, and 2-bits for a mantissa field.

5. The system of claim 1 , wherein each floating-point format of the group of floating-point formats utilizes a same total number of bits for representing a floating point number and a different number of bits for a mantissa field of the floating point number.

6. The system of claim 1 , wherein the specified bias is set using a register argument stored in a register of the microprocessor system.

7. The system of claim 1 , wherein the specified bias is selected from a non-consecutive set of pre-determined floating-point exponent biases.

8. The system of claim 1 , wherein the control unit is configured to reconfigure the configurable bias via a subsequent matrix processor instruction.

9. The system of claim 1 , wherein each of the one or more processing elements includes a floating-point multiplier and an accumulator.

10. The system of claim 1 , wherein each processing element of the one or more processing elements is configured to perform a floating-point multiplication operation in parallel with the other processing elements.

11. The system of claim 1 , wherein the matrix processor instruction specifies a designated accumulator for storing intermediate results of the matrix computational unit.

12. A microprocessor system, comprising:
a matrix processor, wherein the matrix processor is configured to receive a matrix processor instruction that specifies a floating-point operand formatted with an exponent that has been biased with a specified bias, wherein the floating-point operand is a matrix, wherein the matrix processor instruction specifies a floating-point number format for the floating-point operand from a group of floating-point formats, and
wherein the specified bias is configurable based on the matrix processor instruction;
a post-processing unit;
a control unit configured to provide a post-processing instruction to the post-processing unit and the matrix processor instruction to the matrix processor; and
a post-processing register file, wherein the post-processing instruction specifies an operand stored in the post-processing register file.

13. The system of claim 12 , wherein the post-processing unit is a vector computational unit.

14. The system of claim 12 , wherein the operand is a vector operand and the post-processing instruction specifies a data size for each vector element of the operand.

15. A method comprising:
receiving a matrix processor instruction from a control unit, wherein the matrix processor instruction specifies a floating-point operand formatted with an exponent that has been biased with a specified bias, wherein the floating-point operand is a matrix, wherein the matrix processor instruction specifies a floating-point number format for the floating-point operand from a group of floating-point formats, and wherein the specified bias is configurable based on the matrix processor instruction;
issuing one or more reads for data values of the floating-point operand;
receiving the data values of the floating-point operand; and
loading one or more received data values into a matrix computational unit.

Assignees

• Tesla Inc

Inventors

• Das Sarma Debjit
• Mcgee William
• Talpes Emil

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N20/00

  Machine learning · CPC title

• G06N3/08

  Learning methods · CPC title