Hybrid memory module with improved inter-memory data transmission path

Patent metadata

Field	Value
Publication number	US-11226897-B2
Application number	US-202016856820-A
Country	US
Kind code	B2
Filing date	Apr 23, 2020
Priority date	Oct 15, 2015
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.

First claim

What is claimed is:

1. A memory module comprising:
a volatile memory device;
a data buffer;
a non-volatile memory device coupled to the data buffer via a first transmission path, the first transmission path to transfer data between the volatile memory device and the data buffer in a first mode; and
a memory controller device to control the non-volatile memory device, wherein the memory controller device is coupled to the volatile memory device via a second transmission path, the second transmission path to transfer data between the volatile memory device and the memory controller device in a second mode, wherein the data buffer is powered off during the second mode.

2. The memory module of claim 1 , wherein the volatile memory device is a dual-port dynamic random access memory (DRAM) device, wherein the dual-port DRAM device comprises:
a first port coupled to the first transmission path; and
a second port coupled to the second transmission path.

3. The memory module of claim 2 , wherein the first port is not used and the second port is used when transferring the data between the volatile memory device and the memory controller device.

4. The memory module of claim 1 , further comprising a command buffer coupled to the data buffer, the memory controller device, and the volatile memory device.

5. The memory module of claim 4 , wherein the memory controller device, responsive to an event signal, is to:
send a register setting to the command buffer, the register setting being associated with a backup operation in the second mode; and
send a command associated with the backup operation to the command buffer.

6. The memory module of claim 4 , wherein the memory controller device, responsive to an event signal, is to:
send a register setting to the command buffer, the register setting being associated with a restore operation in the second mode; and
send a command associated with the restore operation to the command buffer.

7. The memory module of claim 1 , further comprising a command buffer coupled to the data buffer, the memory controller device, and the volatile memory device, wherein the command buffer is to:
receive a first command from a host memory controller coupled to the memory module in the first mode;
send the first command to the volatile memory device in the first mode;
receive a second command from the memory controller device in the second mode; and
send the second command to the volatile memory device in the second mode.

8. The memory module of claim 7 , wherein the second command is associated with at least one of a backup operation or a restore operation.

9. The memory module of claim 1 , further comprising a command buffer coupled to the data buffer, the memory controller device, and the volatile memory device, wherein the command buffer is to:
receive a first command from a host memory controller coupled to the memory module in the first mode;
send the first command to the volatile memory device in the first mode;
receive a second command from the memory controller device in the second mode;
replicate the second command into a plurality of commands in the second mode; and
send the plurality of commands to the volatile memory device in the second mode.

10. The memory module of claim 1 , wherein the volatile memory device is to enter a mode where a delay locked loop is turned off during a backup operation or a restore operation during the second mode.

11. The memory module of claim 1 , wherein the second mode is a memory controller device control mode that is invoked in response to at least one of a data backup event or a data restore event.

12. The memory module of claim 1 , wherein the second transmission path is to transmit one or more electronic signals between the volatile memory device and the memory controller device in the second mode, wherein the one or more electronic signals comprise at least one of a data signal, a chip select signal, or a data strobe signal.

13. A memory module comprising:
a data buffer;
a flash memory device;
a dual-port dynamic random access memory (DRAM) device; and
a memory controller device to control the flash memory device and coupled to a first port of the dual-port DRAM device via a direct data transmission path, wherein a second port of the dual-port DRAM device is coupled to the data buffer, wherein data transferred between the dual-port DRAM device and the memory controller device over the direct data transmission path bypasses the data buffer, and wherein the data buffer is powered off during at least one of a backup operation or a restore operation on the memory module.

14. The memory module of claim 13 , further comprising a command buffer coupled to the data buffer, the memory controller device, and the dual-port DRAM device.

15. The memory module of claim 14 , wherein the memory controller device, responsive to an event signal, is to:
send a register setting to the command buffer, the register setting being associated with the at least one of the backup operation or the restore operation; and
send, to the command buffer, a command associated with the at least one of the backup operation or the restore operation.

16. The memory module of claim 13 , further comprising a command buffer coupled to the data buffer, the memory controller device, and the dual-port DRAM device, wherein the command buffer is to:
receive a first command from a host memory controller coupled to the memory module;
send the first command to the dual-port DRAM device;
receive a second command from the memory controller device, the second command being associated with the at least one of the backup operation or the restore operation; and
send the second command to the dual-port DRAM device.

17. The memory module of claim 13 , further comprising a command buffer coupled to the data buffer, the memory controller device, and the dual-port DRAM device, wherein the command buffer is to:
receive a first command from a host memory controller coupled to the memory module;
send the first command to the dual-port DRAM device;
receive a second command from the memory controller device, the second command being associated with the at least one of the backup operation or the restore operation;
replicate the second command into a plurality of commands; and
send the plurality of commands to the dual-port DRAM device.

18. A memory module comprising:
a non-volatile memory device;
a dual-port volatile memory device;
a data bus comprising a data buffer; and
a memory controller device to control the non-volatile memory device and coupled to a first port of the dual-port volatile memory device via a direct data transmission path, wherein a second port of the dual-port volatile memory device is coupled to the data buffer, wherein data transferred from the dual-port volatile memory device to the non-volatile memory device over the direct data transmission path or from the non-volatile memory device to the dual-port volatile memory device over the direct data transmission path bypasses the data buffer, and wherein the data buffer of the data bus is powered off during at least one of a backup operation or a restore operation on the memory module.

19. The memory module of claim 18 , further comprising a command buffer coupled to the data buffer, the memory controller device, and the dual-port volatile memory device, wherein the command buffer is to:
receive a first command from a host memory controller coupled to the memory module;
send the first command to the dual-port vola

Assignees

• Rambus Inc

Inventors

• Shallal Aws

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F11/14

  Error detection or correction of the data by redundancy in operations (error detection or correction of the data by redundancy in hardware G06F11/16) · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F11/1441

  Resetting or repowering · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title