Circuit board

Patent metadata

Field	Value
Publication number	US-11224123-B2
Application number	US-202117226389-A
Country	US
Kind code	B2
Filing date	Apr 9, 2021
Priority date	Oct 10, 2018
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

The disclosure provides a circuit board that includes: a carrier element having a number of circuit board layers; a number of electronic components; a number of thermal interfaces; and a number of electrical interfaces. The electronic components are arranged directly on at least one of the surface sides on the carrier element. The opposite surface side of the carrier element is of potential-free design. Additionally, the circuit board with the electronic components is overlaid by a covering material in such a way that the electronic components are mechanically stabilized and the thermal and/or electrical interfaces are free of the covering material.

First claim

What is claimed is:

1. A circuit board, comprising at least:
a carrier element having a number of circuit board layers,
a number of electronic components,
a number of thermal interfaces and
a number of electrical interfaces,
wherein the electronic components are arranged directly on at least one of the surface sides on the carrier element, and
the opposite surface side of the carrier element is of potential-free design, and
wherein the circuit board with the electronic components is overlaid by a covering material in such a way that the electronic components are mechanically stabilized and the thermal and/or electrical interfaces are free of the covering material.

2. The circuit board as claimed in claim 1 , wherein the covering material is a thermoset material.

3. The circuit board as claimed in claim 1 , wherein the covering material has a thickness of at least 1 mm.

4. The circuit board as claimed in claim 1 , wherein the carrier element defines passage bores.

5. The circuit board as claimed in claim 4 , wherein the passage bores include metallized passage bores and/or vertical interconnect accesses.

6. The circuit board as claimed in claim 5 , wherein the passage bores and/or the vertical interconnect accesses each merge with a depth-controlled counterbore, which has a larger diameter than the passage bore or vertical interconnect access in question, at least at one end in a region of one of the surface sides of the circuit board.

7. The circuit board as claimed in claim 4 , wherein at least one of the passage bores is formed at at least one end with a depth-controlled counterbore.

8. The circuit board as claimed in claim 1 , wherein the thermal interfaces are designed on a potential-free surface side as refined, tin-plated, gold-plated or silver-plated, copper areas.

9. The circuit board as claimed in claim 1 , wherein at least one heat-removal area is arranged in at least one inner circuit board layer beneath electronic components with a high thermal output.

10. The circuit board as claimed in claim 1 , wherein at least one test point is arranged in an inner circuit board layer as an electrical interface.

11. The circuit board as claimed in claim 1 , wherein at least one active element, one passive element and/or one microprocessor are/is provided as electronic components.

12. The circuit board as claimed in claim 1 , wherein a sensor and/or a plug are additionally arranged on at least one of the surface sides.

13. The circuit board as claimed in claim 1 , wherein at least one protective area is designed as a lightning arrester and ESD protection in a surface region of the circuit board.

Assignees

• Vitesco Technologies Germany Gmbh

Inventors

• Rumrich Thomas
• Heckel Markus
• Sauerbier Jürgen
• Bock Johannes
• Hornberger Juergen

Classifications

• H05K5/0082

  specially adapted for transmission control units, e.g. gearbox controllers · CPC title

• H05K2203/1327

  Moulding over PCB locally or completely · CPC title

• H05K2201/09518

  Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer · CPC title

• H05K1/0259

  Electrostatic discharge [ESD] protection · CPC title

• H05K1/0271 Primary

  Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion · CPC title