Scaler, display device and associated data processing method

Patent metadata

Field	Value
Publication number	US-11223749-B1
Application number	US-202117332973-A
Country	US
Kind code	B1
Filing date	May 27, 2021
Priority date	Jul 9, 2020
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A scaler includes an input interface, an output Vsync pulse generating circuit and a data buffer circuit. The input interface is arranged to receive an input Vsync pulse and input image data. The output Vsync pulse generating circuit is arranged to accordingly generate a first output Vsync pulse and a first output request in response to the input Vsync pulse. The data buffer circuit is arranged to buffer the input image data and, in response to the first output request, output a first output frame according to the input image data. The output Vsync pulse generating circuit further generates a second output Vsync pulse and a second output request according to the first output Vsync pulse and a first predetermined period and in response to the second output request, the data buffer circuit further outputs a second output frame according to the input image data.

First claim

What is claimed is:

1. A scaler, comprising:
an input interface, arranged to receive an input vertical synchronization pulse and input image data;
an output vertical synchronization pulse generating circuit, coupled to the input interface and arranged to accordingly generate a first output vertical synchronization pulse and a first output request in response to the input vertical synchronization pulse; and
a data buffer circuit, arranged to buffer the input image data and, in response to the first output request, output a first output frame according to the input image data,
wherein the output vertical synchronization pulse generating circuit is further arranged to generate a second output vertical synchronization pulse and a second output request according to the first output vertical synchronization pulse and a first predetermined period, and, in response to the second output request, the data buffer circuit is further arranged to output a second output frame according to the input image data.

2. The scaler of claim 1 , wherein the input image data comprises an input frame, and the data buffer circuit is arranged to output the input frame as the first output frame in response to the first output request and output the input frame as the second output frame in response to the second output request.

3. The scaler of claim 2 , wherein the input frame corresponds to an input frame rate, the first output frame corresponds to a first output frame rate, the second output frame corresponds to a second output frame rate, and the first output frame rate and the second output frame rate are higher than the input frame rate.

4. The scaler of claim 3 , wherein the output vertical synchronization pulse generating circuit is further arranged to generate a third output vertical synchronization pulse and a third output request according to the second output vertical synchronization pulse and a second predetermined period, and, in response to the third output request, the data buffer circuit is further arranged to output the input frame as a third output frame.

5. The scaler of claim 4 , wherein the third output frame corresponds to a third output frame rate and the third output frame rate is higher than the input frame rate.

6. A display device, comprising:
a scaler, arranged to receive an input vertical synchronization pulse and input image data from an image source, generate a plurality of output vertical synchronization pulses according to the input vertical synchronization pulse and generate a plurality of output frames according to the input image data; and
a display panel, coupled to the scaler, arranged to display the output frames according to the output vertical synchronization pulses,
wherein the output vertical synchronization pulses comprise at least a first output vertical synchronization pulse and a second output vertical synchronization pulse, the output frames comprise at least a first output frame and a second output frame, the scaler is arranged to accordingly generate the first output vertical synchronization pulse in response to the input vertical synchronization pulse and accordingly output the first output frame in response to the first output vertical synchronization pulse, and
the scaler is further arranged to generate the second output vertical synchronization pulse according to the first output vertical synchronization pulse and a first predetermined period, and accordingly output the second output frame in response to the second output vertical synchronization pulse.

7. The display device of claim 6 , wherein the first output frame and the second output frame are the same.

8. The display device of claim 6 , wherein the input image data comprises an input frame, the input frame corresponds to an input frame rate, the first output frame corresponds to a first output frame rate, the second output frame corresponds to a second output frame rate, and the first output frame rate and the second output frame rate are higher than the input frame rate.

9. The display device of claim 8 , wherein the output vertical synchronization pulses further comprise a third output vertical synchronization pulse, the output frames further comprise a third output frame, the scaler is further arranged to generate the third output vertical synchronization pulse according to the second output vertical synchronization pulse and a second predetermined period, and accordingly output the third output frame in response to the third output vertical synchronization pulse.

10. The display device of claim 9 , wherein the second predetermined period corresponds to a frame rate supported by the display panel.

11. The display device of claim 6 , wherein the first predetermined period corresponds to a frame rate supported by the display panel.

12. A data processing method, comprising:
receiving an input vertical synchronization pulse and input image data from an image source;
generating a plurality of output vertical synchronization pulses according to the input vertical synchronization pulse; and
generating a plurality of output frames according to the input image data,
wherein the output vertical synchronization pulses comprise at least a first output vertical synchronization pulse and a second output vertical synchronization pulse, the input image data comprises an input frame, the output frames comprise at least a first output frame and a second output frame, and step of generating the output vertical synchronization pulses according to the input vertical synchronization pulse further comprises:
accordingly generating the first output vertical synchronization pulse in response to the input vertical synchronization pulse; and
generating the second output vertical synchronization pulse according to the first output vertical synchronization pulse and a first predetermined period, and
wherein step of generating the output frames according to the input image data further comprises:
accordingly outputting the input frame as the first output frame in response to the first output vertical synchronization pulse; and
accordingly outputting the input frame as the second output frame in response to the second output vertical synchronization pulse.

13. The data processing method of claim 12 , wherein the input frame corresponds to an input frame rate, the first output frame corresponds to a first output frame rate, the second output frame corresponds to a second output frame rate, and the first output frame rate and the second output frame rate are higher than the input frame rate.

14. The data processing method of claim 12 , wherein the output vertical synchronization pulses further comprise a third output vertical synchronization pulse, the output frames further comprise a third output frame, and step of generating the output vertical synchronization pulses according to the input vertical synchronization pulse further comprises:
generating the third output vertical synchronization pulse according to the second output vertical synchronization pulse and a second predetermined period, and wherein step of generating the output frames according to the input image data further comprises:
outputting the input frame as the third output frame in response to the third output vertical synchronization pulse.

15. The data processing method of claim 14 , wherein the input frame corresponds to an input frame rate, the first output frame corresponds to a first output frame rate, the second output frame corresponds to a second output frame rate, the third output frame corresponds to a third output frame rate, and the first output frame rate, the second output

Assignees

• Realtek Semiconductor Corp

Inventors

• Lin Ying-Hsin
• Kung Wen-Hsia
• Chan Chun-Chieh

Classifications

• G09G2360/18

  Use of a frame buffer in a display terminal, inclusive of the display panel · CPC title

• G09G5/12

  Synchronisation between the display unit and other units, e.g. other display units, video-disc players · CPC title

• G09G5/006

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• H04N5/04 Primary

  Synchronising (for television systems using pulse code modulation H04N7/56) · CPC title