Signal receiver circuit, and semiconductor apparatus and semiconductor system including the signal receiver circuit

Patent metadata

Field	Value
Publication number	US-11223503-B2
Application number	US-201916572154-A
Country	US
Kind code	B2
Filing date	Sep 16, 2019
Priority date	Feb 26, 2019
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A signal receiver circuit includes a first amplification circuit and an offset compensation circuit. The first amplification circuit generates a first amplified signal and a second amplified signal by amplifying an input signal and a reference voltage. The offset compensation circuit adjusts voltage levels of the first and second amplified signals based on a DC level of the input signal and a voltage level of the reference voltage.

First claim

What is claimed is:

1. A signal receiver circuit comprising:
a first amplification circuit configured to amplify an input signal and a reference voltage to output a first amplified signal through a first amplification node and output a second amplified signal through a second amplification node;
a voltage adjusting circuit configured to change a voltage level of the first amplified signal based on the second amplified signal and a first bias signal, and change a voltage level of the second amplified signal based on the first amplified signal and a second bias signal; and
a bias signal generation circuit configured to compare a DC (direct current) level of the input signal and the reference voltage to generate the first bias signal and the second bias signal,
wherein the DC level of the input signal is a middle voltage level between a maximum voltage and a minimum voltage of the input signal.

2. The signal receiver circuit according to claim 1 , wherein the bias signal generation circuit generates the first bias signal to have a higher voltage level than a voltage level of the second bias signal when the DC level of the input signal is higher than the reference voltage, and
the bias signal generation circuit generates the first bias signal to have a lower voltage level than the voltage level of the second bias signal when the DC level of the input signal is lower than the reference voltage.

3. The signal receiver circuit according to claim 1 , wherein the voltage adjusting circuit comprises:
a cross-coupling circuit configured to couple the second amplification node and a first discharge node based on the first amplified signal, and couple the first amplification node and a second discharge node based on the second amplified signal;
a first current circuit configured to adjust an amount of current flowing from the first discharge node to a power supply voltage terminal based on the second bias signal; and
a second current circuit configured to adjust an amount of current flowing from the second discharge node to the power supply voltage terminal based on the first bias signal.

4. The signal receiver circuit according to claim 1 , wherein the voltage adjusting circuit comprises:
a first transistor coupled between the second amplification node and a first discharge node, and having a gate which is coupled with the first amplification node;
a second transistor coupled between the first amplification node and a second discharge node, and having a gate which is coupled with the second amplification node;
a third transistor coupled between the first discharge node and a power supply voltage terminal, and having a gate which receives the second bias signal; and
a fourth transistor coupled between the second discharge node and the power supply voltage terminal, and having a gate which receives the first bias signal.

5. The signal receiver circuit according to claim 1 , wherein the bias signal generation circuit comprises:
a DC level detector configured to detect a DC level of the input signal to generate a DC level signal; and
a bias voltage generator configured to compare the DC level signal and the reference voltage to generate the first bias signal and the second bias signal.

6. The signal receiver circuit according to claim 1 , wherein the bias signal generation circuit comprises:
a DC level selector configured to generate a plurality of divided voltages, and output at least one of the plurality of divided voltages as a DC level signal based on a select signal generated based on a characteristic of a channel through which the input signal is transmitted; and
a bias voltage generator configured to compare the DC level signal and the reference voltage to generate the first bias signal and the second bias signal.

7. The signal receiver circuit according to claim 1 ,
wherein the bias signal generation circuit further generates a current code signal, and
wherein the voltage adjusting circuit comprises:
a cross-coupling circuit configured to couple the second amplification node and a first discharge node based on the first amplified signal, and couple the first amplification node and a second discharge node based on the second amplified signal;
a first variable current circuit configured to adjust an amount of current flowing from the first discharge node to a power supply voltage terminal based on the current code signal and the second bias signal; and
a second variable current circuit configured to adjust an amount of current flowing from the second discharge node to the power supply voltage terminal based on the current code signal and the first bias signal.

8. The signal receiver circuit according to claim 1 , further comprising:
a second amplification circuit configured to amplify the first amplified signal and the second amplified signal to generate a first output signal and a second output signal.

9. A signal receiver circuit comprising:
a first amplification circuit configured to amplify an input signal and a reference voltage to generate a first amplified signal through a first amplification node and generate a second amplified signal through a second amplification node;
a second amplification circuit configured to amplify the first amplified signal and the second amplified signal to generate a first output signal and a second output signal;
a bias signal generation circuit configured to compare a DC (direct current) level of the input signal and the reference voltage to generate a first bias signal and a second bias signal; and
a voltage adjusting circuit configured to change voltage levels of the first and second amplified signals based on the first amplified signal, the second amplified signal, the first bias signal and the second bias signal,
wherein the DC level of the input signal is a middle voltage level between a maximum voltage and a minimum voltage of the input signal.

10. The signal receiver circuit according to claim 9 , wherein the bias signal generation circuit generates the first bias signal to have a higher voltage level than a voltage level of the second bias signal when the DC level of the input signal is higher than the reference voltage, and
the bias signal generation circuit generates the first bias signal to have a lower voltage level than the voltage level of the second bias signal when the DC level of the input signal is lower than the reference voltage.

11. The signal receiver circuit according to claim 9 , wherein the bias signal generation circuit comprises:
a DC level detector configured to generate a DC level signal by detecting a DC level of the input signal; and
a bias voltage generator configured to generate the first bias signal and the second bias signal by comparing the DC level signal and the reference voltage.

12. The signal receiver circuit according to claim 9 , wherein the bias signal generation circuit comprises:
a DC level selector configured to generate a plurality of divided voltages, and output at least one of the plurality of divided voltages as a DC level signal based on a select signal generated based on a characteristic of a channel through which the input signal is transmitted; and
a bias voltage generator configured to generate the first bias signal and the second bias signal by comparing the DC level signal and the reference voltage.

13. The signal receiver circuit according to claim 9 , wherein the voltage adjusting circuit changes a voltage level of the first amplified signal based on the first bias signal and the second amplified signal, and changes a voltage level of the second amplified signal based on the second bias signal and the first amplified signal.

Assignees

• Sk Hynix Inc

Inventors

• Kang Ji Hyo

Classifications

• H03F3/45968

  by offset reduction · CPC title

• H03F3/45995

  using switching means · CPC title

• H04L25/0296 Primary

  Arrangements to ensure DC-balance · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F3/45179 Primary

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title