Phase-locked loop circuitry and method to prevent fractional N spurious outputs in radar phase-locked loop

Patent metadata

Field	Value
Publication number	US-11223364-B2
Application number	US-201916676869-A
Country	US
Kind code	B2
Filing date	Nov 7, 2019
Priority date	Nov 7, 2019
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A signal generator includes a first phase-locked loop (PLL) configured to receive a first reference signal having a first reference frequency and generate a ramping signal based on the first reference signal, where the ramping signal is between a minimum frequency and a maximum frequency of a radar frequency band; a system clock configured to generate a second reference signal having a common system reference frequency; and a second PLL configured to receive the second reference signal from the system clock, generate the first reference signal based on the second reference signal, and provide the first reference signal to the first PLL.

First claim

What is claimed is:

1. A signal generator, comprising:
a first phase-locked loop (PLL) configured to receive a first reference signal having a first reference frequency and generate a ramping signal based on the first reference signal, wherein the ramping signal is between a minimum frequency and a maximum frequency of a radar frequency band;
a system clock configured to generate a second reference signal having a common system reference frequency; and
a second PLL configured to receive the second reference signal from the system clock, generate the first reference signal based on the second reference signal, and provide the first reference signal to the first PLL.

2. The signal generator of claim 1 , wherein the first PLL is configured to generate a first PLL signal based on the ramping signal, compare the first PLL signal and the first reference signal to generate a first error signal, and generate the ramping signal based on the first error signal.

3. The signal generator of claim 2 , wherein the first PLL comprises:
a multi-modulus divider (MMD) configured to generate the first PLL signal based on the ramping signal,
wherein the radar frequency band defined by the minimum frequency and the maximum frequency is substantially free of any fractional spurs caused by the MMD.

4. The signal generator of claim 2 , wherein:
the second PLL is configured to generate a second PLL signal based on the first reference signal and the second reference signal, generate a third reference signal based on the second reference signal, compare the second PLL signal and the third reference signal to generate a second error signal, and generate the first reference signal based on the second error signal.

5. The signal generator of claim 4 , wherein:
the first PLL comprises a negative feedback path and a multi-modulus divider (MMD) in the negative feedback path, the MMD being configured to generate the first PLL signal, and
the radar frequency band is substantially free of any fractional spurs caused by the MMD.

6. The signal generator of claim 5 , wherein the MMD is configured to generate the minimum frequency based on a first fractional value and generate the maximum frequency based on a second fractional value, wherein the first fractional value and the second fractional value are between two consecutive integers, including a lower integer and a higher integer, with a first margin between the lower integer and the first fractional value and a second margin between the second fractional value and the higher integer.

7. The signal generator of claim 6 , wherein the first and second margins correspond to a frequency of at least 100 MHz in the frequency domain.

8. The signal generator of claim 4 , wherein the second PLL comprises:
a mixer configured to receive the first reference signal and the second reference signal, and generate a down-mixed signal as the second PLL signal; and
a first fixed frequency divider configured to receive the second reference signal and convert the second reference signal into a second frequency-reduced reference signal as the third reference signal.

9. The signal generator of claim 1 , wherein:
the first PLL is configured to generate a first PLL signal based on the ramping signal, compare the first PLL signal and the first reference signal to generate a first error signal, and generate the ramping signal based on the first error signal,
the second PLL is configured to generate a second PLL signal based on the first reference signal and the second reference signal, compare the second PLL signal and the second reference signal to generate a second error signal, and generate the first reference signal based on the second error signal, and
the second PLL comprises:
a first fixed frequency divider configured to receive the first reference signal and convert the first reference signal into a first frequency-reduced reference signal; and
a mixer configured to receive the frequency-reduced reference signal and the second reference signal, and generate a down-mixed signal as the second PLL signal.

10. The signal generator of claim 4 , wherein the second PLL comprises:
a first controlled oscillator configured to generate the first reference signal based on a first control signal;
a mixer configured to receive the first reference signal and the second reference signal, and generate a down-mixed signal as the second PLL signal;
a first fixed frequency divider configured to receive the second reference signal and convert the second reference signal into a second frequency-reduced reference signal as the third reference signal;
a first phase frequency detector (PFD) configured to generate the second error signal by comparing the second PLL signal and the third reference signal; and
a first loop filter configured to generate the first control signal based on the second error signal.

11. The signal generator of claim 1 , wherein:
the first PLL is configured to generate a first PLL signal based on the ramping signal, compare the first PLL signal and the first reference signal to generate a first error signal, and generate the ramping signal based on the first error signal,
the second PLL is configured to generate a second PLL signal based on the first reference signal and the second reference signal, compare the second PLL signal and the second reference signal to generate a second error signal, and generate the first reference signal based on the second error signal, and
the second PLL comprises:
a first controlled oscillator configured to generate the first reference signal based on a first control signal;
a first fixed frequency divider configured to receive the first reference signal from the first controlled oscillator and convert the first reference signal into a first frequency-reduced reference signal;
a mixer configured to receive the frequency-reduced reference signal and the second reference signal, and generate a down-mixed signal as the second PLL signal;
a first phase frequency detector (PFD) configured to generate the second error signal by comparing the second PLL signal and the second reference signal; and
a first loop filter configured to generate the first control signal based on the second error signal.

12. The signal generator of claim 1 , wherein the second PLL is an entirely digital circuit.

13. The signal generator of claim 12 , wherein the second PLL is configured to output a single-frequency signal, wherein the single-frequency signal is the first reference signal.

14. The signal generator of claim 1 , wherein the ramping signal is a frequency-modulated continuous-wave (FMCW) radar signal.

15. A method of preventing fractional spurs inside a radar frequency band having a frequency range including a minimum frequency and a maximum frequency, the method comprising:
generating, by a first phase-locked loop (PLL), a ramping signal within the radar frequency band based on a first reference signal;
generating, by a system clock, a second reference signal having a common system reference frequency;
generating, by a second PLL, the first reference signal based on the second reference signal; and
transmitting, by the second PLL, the first reference signal to the first PLL.

16. The method of claim 15 , further comprising:
generating, by the first PLL, a first PLL signal based on the ramping signal;
generating, by the first PLL, a first error signal by comparing the first PLL signal and the first reference signal; and
generating, by the first PLL, the ramping signal based on the first error signal.

17. The method of cla

Assignees

• Infineon Technologies Ag

Inventors

• Itkin Grigory

Classifications

• H03L7/091 Primary

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/12

  using a scanning signal · CPC title

• H03L7/185

  using a mixer in the loop (H03L7/187 - H03L7/195 take precedence) · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title