Inverter stacking amplifier

Patent metadata

Field	Value
Publication number	US-11223335-B2
Application number	US-201816614625-A
Country	US
Kind code	B2
Filing date	Jun 4, 2018
Priority date	Jun 2, 2017
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

The exemplified disclosure presents a highly power efficient amplifier (e.g., front-end inverter and/or amplifier) that achieves significant current reuse (e.g., 6-time for a 3-stack embodiments) by stacking inverters and splitting the capacitor feedback network. In some embodiments, the exemplified technology facilitates N-time current reuse to substantially reduced power consumption. It is observed that the exemplified disclosure facilitates significant current-reuse operation that significantly boost gain gm while providing low noise performance without increasing power usage. In addition, the exemplified technology is implemented such that current reuse and number of transistor has a generally linear relationship and using fewer transistors as compared to known circuits of similar topology.

First claim

What is claimed is:

1. An apparatus comprising an array of N stacked inverters having capacitive feedback split across N feedback paths to provide 2N-time current reuse for a single channel input, the apparatus comprising:
an array of inverter-based transconductors comprising a first inverter-based transconductor and a second inverter-based transconductor vertically stacked with respect to the first inverter-based transconductor, the array of inverter-based transconductors being coupled to a summing circuit configured to combine currents outputted from each respective inverter-based transconductor of the array; and
a capacitive feedback network comprising a plurality of capacitive elements, wherein the capacitive feedback network is coupled to the combined current outputs of the array of inverter-based transconductor and is split into paths corresponding to a number of inverter-based transconductor in the array such that a voltage input stage of the array of inverter-based transconductor is AC-coupled to each invertor-based transconductor stage of the array.

2. The apparatus of claim 1 , wherein the array of inverter-based transconductors comprises
a third inverter-based transconductor, the third inverter-based transconductor being vertically stacked with respect to the first inverter-based transconductor, the third inverter-based transconductor being coupled to a common-gate transistors of the plurality of common-gate transistors to combine current outputted from the third inverter-based transconductor along with the current output of the first and second inverter-based transconductors.

3. The apparatus of claim 1 , wherein the apparatus is configured to generate 2N times current reuse for an N-stage inverter-based transconductor array.

4. The apparatus of claim 3 , wherein the apparatus is configured to generate 6 times current reuse for a 3-stage inverter-based transconductor array.

5. The apparatus of claim 1 , wherein the summing circuit comprises a plurality of common-gate transistors configured to combine currents outputted from each respective inverter-based transconductor of the array.

6. The apparatus of claim 3 , wherein the N-stage inverter-based transconductor array is selected from the group consisting of a 2-stage inverter-based transconductor array, a 3-stage inverter-based transconductor array, a 4-stage inverter-based transconductor array, a 5-stage inverter-based transconductor array, and a 6-stage inverter-based transconductor array.

7. The apparatus of claim 1 , wherein each inverter-based transconductor of the array comprises an N-MOS pair forming a top inverter and a P-MOS pair coupled to the N-MOS pair to form a bottom inverter.

8. The apparatus of claim 1 , wherein the invertor-based transconductor stage is configured to receive a differential-mode input.

9. The apparatus of claim 1 , wherein connection nodes between the first inverter-based transconductor and a second inverter-based transconductor are used as a virtual ground.

10. The apparatus of claim 1 , wherein the invertor-based transconductor stage is configured to receive a common-mode input.

11. The apparatus of claim 1 , wherein the apparatus is configured to generate a gain of an input signal between about 25.4 dB and about 25.6 dB with about 0.23 μW and 0.25 μW of power.

12. The apparatus of claim 1 , wherein the array of inverter-based transconductors has N outputs corresponding to an N number of inverter stages.

13. The apparatus of claim 1 , comprising a first current source and a second current source, the first and second current sources being coupled to a top node and a bottom node array of inverter-based transconductors to isolate the array from respective power lines.

14. The apparatus of claim 1 , wherein the array of inverter-based transconductors is coupled to a same single power supply.

15. The amplifier of claim 1 , wherein the apparatus forms an integrated circuit.

16. An amplifier comprising:
an array of N stacked inverters having capacitive feedback split across N feedback paths to provide 2N-time current reuse for a single channel input, each N stack inverter of the array comprising an inverter-based transconductors vertically stacked with respect to each other, the array of inverter-based transconductors being coupled to a summing circuit configured to combine currents outputted from each respective inverter-based transconductor of the array; and
a capacitive feedback network comprising a plurality of capacitive elements, wherein the capacitive feedback network is coupled to the combined current outputs of the array of inverter-based transconductor and is split into paths corresponding to a number of inverter-based transconductor in the array such that a voltage input stage of the array of inverter-based transconductor is AC-coupled to each invertor-based transconductor stage of the array.

17. The amplifier of claim 16 , wherein the amplifier is configured to generate 2N times current reuse for an N-stage inverter-based transconductor array.

18. The amplifier of claim 16 , wherein the array of inverter-based transconductors has N outputs corresponding to an N number of inverter stages.

19. A system comprising:
a sensor; and
an amplifier, the amplifier comprising an array of N stacked inverters having capacitive feedback split across N feedback paths to provide 2N-time current reuse for a single channel input, each N stack inverter of the array comprising an inverter-based transconductors vertically stacked with respect to each other, the array of inverter-based transconductors being coupled to a summing circuit configured to combine currents outputted from each respective inverter-based transconductor of the array; and
a capacitive feedback network comprising a plurality of capacitive elements, wherein the capacitive feedback network is coupled to the combined current outputs of the array of inverter-based transconductor and is split into paths corresponding to a number of inverter-based transconductor in the array such that a voltage input stage of the array of inverter-based transconductor is AC-coupled to each invertor-based transconductor stage of the array.

20. The system of claim 19 , wherein the amplifier is configured to generate 2N times current reuse for an N-stage inverter-based transconductor array.

Assignees

• Univ Texas

Inventors

• Sun Nan
• Shen Linxiao

Classifications

• H03F2203/45548

  the IC comprising one or more capacitors as shunts to earth or as short circuit between inputs · CPC title

• H03G1/0029

  using field-effect transistors [FET] · CPC title

• H03F3/3015

  using a common source driving stage, i.e. inverting stage · CPC title

• H03F1/3211

  in differential amplifiers · CPC title

• H03F2203/45544

  the IC comprising one or more capacitors, e.g. coupling capacitors · CPC title