Integrated circuit device and method of manufacturing thereof

Patent metadata

Field	Value
Publication number	US-11222944-B2
Application number	US-201917051916-A
Country	US
Kind code	B2
Filing date	May 2, 2019
Priority date	May 2, 2018
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

An integrated circuit device includes a semiconductor substrate having a resistivity of at least 100 Ω·cm. An electrically insulating layer contacts the semiconductor substrate. The electrically insulating layer is susceptible of inducing in the semiconductor substrate a parasitic surface conduction layer that interfaces with the electrically insulating layer. An electrical circuit is located on the electrically insulating layer. The electrical circuit includes a section capable of inducing an electrical field in the semiconductor substrate. The integrated circuit device includes a depletion-inducing junction of which at least a portion is comprised in the semiconductor substrate. The depletion-inducing junction can autonomously induce in the semiconductor substrate a depleted zone that interfaces with a section of the electrically insulating layer that lies in-between two sections of the electrical circuit.

First claim

The invention claimed is:

1. An integrated circuit device comprising:
a semiconductor substrate having a resistivity of at least 100 Ω·cm;
an electrically insulating layer that contacts the semiconductor substrate, the electrically insulating layer being susceptible of inducing in the semiconductor substrate a parasitic surface conduction layer that interfaces with the electrically insulating layer; and
an electrical circuit located on the electrically insulating layer,
wherein the integrated circuit device comprises a plurality of depletion-inducing junctions at least partially comprised in the semiconductor substrate, the plurality of depletion-inducing junctions being adapted to autonomously induce in the semiconductor substrate a plurality of depleted zones that interface with the electrically insulating layer, whereby the depletion-inducing junctions are disposed in one of the following manners: an array-like manner and a checkerboard-like manner, and whereby at least some depletion-inducing junctions of the plurality interface with a section of the electrically insulating layer that lies in-between two sections of the electrical circuit.

2. An integrated circuit device according to claim 1 , wherein a depletion-inducing junction comprises a doped region in the semiconductor substrate near the electrically insulating layer the doped region having polarity that is opposite to a polarity of free charge carriers in an adjacent region where a bulk section of the semiconductor substrate interfaces with the electrically insulating layer.

3. An integrated circuit device according to claim 2 , wherein the depletion-inducing junction comprises another doped region in the semiconductor substrate near the electrically insulating layer, the one and the other doped region interfacing with each other and having opposite polarities.

4. An integrated circuit device according to claim 1 , wherein a depletion-inducing junction comprises an electrical conductor that traverses the electrically insulating layer and that interfaces with the semiconductor substrate thereby forming a Schottky contact.

5. An integrated circuit device according to claim 1 , comprising a set of electrical contacts through which a biasing voltage can be applied to at least some depletion-inducing junctions of the plurality.

6. An integrated circuit device claim 1 , wherein at least some depletion-inducing junctions of the plurality that are disposed in an array-like manner are further disposed in a loop-like manner surrounding at least one of the two sections of the electrical circuit.

7. A semiconductor wafer adapted for manufacturing an integrated circuit device according to claim 1 , the semiconductor wafer comprising:
a semiconductor substrate having a resistivity of at least 100 Ω·cm;
an electrically insulating layer that contacts the semiconductor substrate, the electrically insulating layer being susceptible of inducing in the semiconductor substrate a parasitic surface conduction layer that interfaces with the electrically insulating layer; and
a semiconductor layer located on the electrically insulating layer in which the electrical circuit can be formed,
wherein the semiconductor wafer comprises a plurality of depletion-inducing junctions at least partially comprised in the semiconductor substrate, the plurality of depletion-inducing junctions being adapted to autonomously induce in the semiconductor substrate a plurality of depleted zones that interface with the electrically insulating layer, whereby the depletion-inducing junctions are disposed in one of the following manners: an array-like manner and a checkerboard-like manner.

8. A method of manufacturing an integrated circuit device according to any of claim 1 , comprising the step of forming a plurality of depletion-inducing junctions at least partially in a semiconductor substrate having a resistivity of at least 100 Ω·cm, the depletion-inducing junctions being formed to autonomously induce in the semiconductor substrate a plurality of depleted zones that interface with a section of an electrically insulating layer susceptible of inducing in the semiconductor substrate a parasitic surface conduction layer that interfaces with the electrically insulating layer, whereby the depletion-inducing junctions are formed so that these are disposed in one of the following manners: an array-like manner and a checkerboard-like manner.

9. A method of manufacturing according to claim 8 , wherein the depletion-inducing junctions are formed using a processing step that is also used to form the electrical circuit.

10. A method of manufacturing according to claim 8 , wherein the depletion-inducing junctions are at least partially formed using at least one of the following techniques: implantation and diffusion.

Assignees

• Univ Catholique Louvain

Inventors

• Raskin Jean-Pierre
• Rack Martin

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W44/501 Primary

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title